Patents by Inventor Matthew Thompson

Matthew Thompson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEMS AND METHODS FOR INTRA-OPERATIVE PELVIC REGISTRATION
    Publication number: 20220125334
    Abstract: A system for intra-operatively registering a pelvis comprising an acetabulum with a computer model of the pelvis in a coordinate system. The system may include: a) a surgical navigation system including a tracking device; and b) at least one computing device in communication with the surgical navigation system. The at least one computing device: i) receiving first data points from first intra-operatively collected points on an articular surface of the acetabulum, the first data points collected with the tracking device; ii) receiving a second data point from a second intra-operatively collected point on the pelvis, the second data point collected with the tracking device, the second data point corresponding in location to a second virtual data point on the computer model; and iii) determining an intra-operative center of rotation of the femur relative to the pelvis from the first data points.
    Type: Application
    Filed: January 11, 2022
    Publication date: April 28, 2022
    Applicant: MAKO Surgical Corp.
    Inventors: Sunil Gupta, Ta-Cheng Chang, Zenan Zhang, Kevin Bechtold, Matthew Thompson, Eric Branch, Varun Chandra, Zhu Wu
  • Cache size change
    Patent number: 11314644
    Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 26, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan
  • Prefetch kill and revival in an instruction cache
    Patent number: 11314660
    Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 26, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Abhijeet Ashok Chachad, Hung Ong
  • Tag update bus for updated coherence state
    Patent number: 11307987
    Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 19, 2022
    Assignee: Texas Instmments Incorporated
    Inventors: Abhijeet Ashok Chachad, David Matthew Thompson, Naveen Bhoria, Peter Michael Hippleheuser
  • Global coherence operations
    Patent number: 11294707
    Abstract: A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 5, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan
  • Subtitle presentation based on volume control
    Patent number: 11290661
    Abstract: Systems and methods are provided for presenting subtitles. The systems and methods include accessing, by a user device, a video discovery graphical user interface that includes a plurality of videos; receiving a user input that gradually reduces volume of the user device; determining that the volume of the user device has gradually been reduced by the user input until a mute state has been reached in which audio output of the user device is disabled; and in response to determining that the volume of the user device has gradually been reduced until the mute state has been reached, automatically causing subtitles of a first video of the plurality of videos to be displayed during playback of the first video.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: March 29, 2022
    Assignee: Snap Inc.
    Inventors: Nathan Kenneth Boyd, Andrew Grosvenor Cooper, David Michael Hornsby, Georgiy Kassabli, Matthew Thompson
  • Presenting content items based on previous reactions
    Patent number: 11288310
    Abstract: Systems and methods are provided for performing operations including: retrieving, by one or more processors, a plurality of content items; identifying a first content item from the plurality of content items to which a user has previously reacted; determining a category of the first content item; selecting a second content item in the plurality of content items that is associated with the determined category of the first content item to which the user has previously reacted; and presenting the second content item to the user in a presentation arrangement of a graphical user interface.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 29, 2022
    Assignee: Snap Inc.
    Inventors: Newar Husam Al Majid, Nathan Kenneth Boyd, Laurent Desserrey, Matthew Thompson, Jeremy Voss
  • Brackets and methods for installing modular, lightweight load-carrying panels and racks on automobiles
    Patent number: 11279421
    Abstract: A pickup full of gear doesn't have to be a jumbled mess. A modular, lightweight load-carrying system is custom engineered to fit directly to each make and model of pickups using the existing OEM mounting points in the bed. The rack systems allow pickup operators to keep gear organized, easily accessible, and secure.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: March 22, 2022
    Assignee: Puteo, Inc.
    Inventors: Seth Hoogendoorn, Conner Schramm, Nicholas Niemeyer, Matthew Thompson, Parker Freeman
  • Sacrificial blade tips for ducted aircraft
    Patent number: 11273910
    Abstract: A proprotor blade for a ducted aircraft including a duct includes a main body having a distal end and a sacrificial blade tip coupled to the distal end of the main body. The sacrificial blade tip includes a deformable core material and a shell layer at least partially covering the deformable core material. The sacrificial blade tip deforms upon contact with the duct, thereby reducing damage to the ducted aircraft.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: March 15, 2022
    Assignee: Textron Innovations Inc.
    Inventors: George Matthew Thompson, Jonathan Andrew Knoll, Nicholas Ralph Carlson, Timothy Brian Carr
  • Electrode layer partitioning
    Patent number: 11268976
    Abstract: A MEMS sensor includes a proof mass that is suspended over a substrate. A sense electrode is located on a top surface of the substrate parallel to the proof mass, and forms a capacitor with the proof mass. The sense electrodes have a plurality of slots that provide improved performance for the MEMS sensor. A measured value sensed by the MEMS sensor is determined based on the movement of the proof mass relative to the slotted sense electrode.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: March 8, 2022
    Assignee: InvenSense, Inc.
    Inventors: Alexander Castro, Matthew Thompson, Leonardo Baldasarre, Sarah Nitzan, Houri Johari-Galle
  • HARDWARE COHERENCE SIGNALING PROTOCOL
    Publication number: 20220066937
    Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.
    Type: Application
    Filed: October 12, 2021
    Publication date: March 3, 2022
    Inventors: Abhijeet Ashok CHACHAD, David Matthew THOMPSON, Naveen BHORIA, Peter Michael HIPPLEHEUSER
  • VTOL Aircraft having Multiple Wing Planforms
    Publication number: 20220063799
    Abstract: An aircraft having multiple wing planforms. The aircraft includes an airframe having first and second half-wings with first and second pylons extending therebetween. A distributed thrust array is attached to the airframe. The thrust array includes a plurality of propulsion assemblies coupled to the first half-wing and a plurality of propulsion assemblies coupled to the second half-wing. A flight control system is coupled to the airframe. The fight control system is configured to independently control each of the propulsion assemblies and control conversions between the wing planforms. The aircraft is configured to convert between thrust-borne lift in a VTOL orientation and wing-borne lift in a forward flight orientation. In addition, the aircraft is configured to convert between a biplane configuration and a monoplane configuration in the forward flight orientation.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 3, 2022
    Applicant: Textron Innovations Inc.
    Inventors: Jonathan Andrew Knoll, George Matthew Thompson, Matthew Edward Louis
  • PREFETCH MANAGEMENT IN A HIERARCHICAL CACHE SYSTEM
    Publication number: 20220058127
    Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.
    Type: Application
    Filed: November 8, 2021
    Publication date: February 24, 2022
    Inventors: Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Abhijeet Ashok Chachad, Hung ONG
  • Error correcting codes for multi-master memory controller
    Patent number: 11249842
    Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 15, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, David Matthew Thompson, Son Hung Tran
  • Dock Management System with GFCI Failure Indication
    Publication number: 20220045501
    Abstract: In a method of warning of a hazardous electrical condition at a dock with wiring coupled to a voltage source via a dock breaker, an electric voltage between a ground and at least one of the dock frame or the water is detected. A plurality of voltage values of the electric voltage is stored. When at least two successive voltage values of the plurality voltage values exceeds a baseline safe voltage by a preset margin, then a shock warning signal is asserted, a dock breaker is opened and a shock warning indication is transmitted to a remote unit via a communication chipset. When at a voltage is sensed in the dock wiring system after the dock breaker has been opened, then a faulty dock breaker warning indication is transmitted to the remote unit via the communication chipset.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 10, 2022
    Inventors: Albert Matthews Thompson, JR., Brandon Loyal Turner, Mark Joseph Gordon, Daniel Steven Haligas, Tom Cullinan
  • Cache coherence shared state suppression
    Patent number: 11243883
    Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 8, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, David Matthew Thompson, Timothy David Anderson, Kai Chirca
  • Pipelined read-modify-write operations in cache memory
    Patent number: 11237905
    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: February 1, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, David Matthew Thompson, Daniel Brad Wu
  • System, Method And Software Program For Aiding In Positioning Of Objects In A Surgical Environment
    Publication number: 20220022994
    Abstract: Systems, methods and software are provided for aiding in positioning of objects in a surgical environment. A tracker is rigidly affixed to a surgical object. A camera has a field of view and senses positions of the tracker in the field of view. Controller(s) provide a zone positioned within the field of view at a location that is static relative to the field of view such that the zone is located independent of the sensed positions of the tracker. The zone defines a range of acceptable positions for the tracker relative to a position of the camera. Controller(s) acquire positions of the tracker as the surgical object is moved throughout a range of motion and enable evaluation of the positions of the tracker throughout the range of motion relative to the zone to aid in positioning of one or more of: the camera, the tracker, or the surgical object.
    Type: Application
    Filed: October 7, 2021
    Publication date: January 27, 2022
    Applicant: MAKO Surgical Corp.
    Inventors: Jason Karl Otto, Matthew Thompson, Mark Ellsworth Nadzadi, Roberto Montane, Jonathan Morgan, Bojan Gospavic
  • Ducted Proprotor Systems Having Adaptive Duct Geometries
    Publication number: 20220024571
    Abstract: A proprotor system for a ducted aircraft convertible between a vertical takeoff and landing flight mode and a forward flight mode includes a plurality of proprotor blades and a duct surrounding the proprotor blades. The duct includes an adaptive geometry device movable into various positions including a hover position and a cruise position. One or more actuators coupled to the adaptive geometry device are configured to move the adaptive geometry device between the hover position and the cruise position based on the flight mode of the ducted aircraft, thereby improving flight performance of the ducted aircraft.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 27, 2022
    Applicant: Textron Innovations Inc.
    Inventors: George Matthew Thompson, Brad Joseph Passe, Nicholas Ralph Carlson
  • MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
    Publication number: 20220027275
    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.
    Type: Application
    Filed: October 4, 2021
    Publication date: January 27, 2022
    Inventors: Abhijeet Ashok Chachad, Timothy David Anderson, Kai Chirca, David Matthew Thompson