Abstract: An embodiment includes a device comprising: a substrate; a dielectric layer on the substrate and including a trench; a first portion of the trench including a first material that comprises at least one of a group III-V material and a group IV material; and a second portion of the trench, located between the first portion and the substrate, which includes a second material and an upper region and a lower region; wherein: (a)(i) the second material in the upper region has fewer defects than the second material in the lower region, and (a)(ii) the first material is strained. Other embodiments are described herein.

Abstract: An apparatus including a transistor device including a body including a channel region between a source region and a drain region; and a gate stack on the body in the channel region, wherein at least one of the source region and the drain region of the body include a contact surface between opposing sidewalls and the contact surface includes a profile such that a height dimension of the contact surface is greater at the sidewalls than at a point between the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body dimension defining a channel region between a source region and a drain region; forming a groove in the body in at least one of the source region and the drain region; and forming a gate stack on the body in the channel region.

Abstract: An apparatus is described. The apparatus includes a FINFET transistor. The FINFET transistor comprises a tapered subfin structure having a sidewall surface area that is large enough to induce aspect ratio trapping of lattice defects along sidewalls of the subfin structure so that the defects are substantially prevented from reaching said FINFET transistor's channel.

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a first metal electrode located in a first metal layer is coupled to a first portion of the channel layer by a first short via, and a second metal electrode located in a second metal layer is coupled to a second portion of the channel layer by a second short via. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

Abstract: Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.

Abstract: A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.

Abstract: Transistor devices having an indium-containing ternary or greater III-V compound active channels, and processes for the fabrication of the same, may be formed that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium-containing ternary or greater III-V compound may be deposited in narrow trenches on a reconstructed upper surface of a sub-structure, which may result in a fin that has indium rich side surfaces and an indium rich bottom surface. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous compositions of indium-containing ternary or greater III-V compound active channels.

Abstract: Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.

Abstract: Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The sub-fin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.

Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.

Abstract: An apparatus including a transistor device disposed on a surface of a circuit substrate, the device including a body including opposing sidewalls defining a width dimension and a channel material including indium, the channel material including a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body including opposing sidewalls and including a buffer material and a channel material on the buffer material, the channel material including indium and the buffer material includes a facet that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls; and forming a gate stack on the channel material.

Abstract: An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

Abstract: Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a sub-structure, e.g. a buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electronic mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure. In a further embodiment, the sub-structure may be removed to form either a void between the active channel and the substrate, or an insulative material may be disposed between the active channel and the substrate, such that the void or the insulative material form an insulative buffer.

Abstract: Disclosed herein are tri-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a fin stack shaped as a fin extending away from a base, and a subfin dielectric stack. The fin includes a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion. The subfin dielectric stack includes a transistor dielectric material, and a fixed charge liner material disposed between the transistor dielectric material and the subfin portion of the fin.

Abstract: Monolithic finFETs including a majority carrier channel in a first III-V compound semiconductor material disposed on a second III-V compound semiconductor. While a mask, such as a sacrificial gate stack, is covering the channel region, a source of an amphoteric dopant is deposited over exposed fin sidewalls and diffused into the first III-V compound semiconductor material. The amphoteric dopant preferentially activates as a donor within the first III-V material and an acceptor with the second III-V material, providing transistor tip doping with a p-n junction between the first and second III-V materials. A lateral spacer is deposited to cover the tip portion of the fin. Source/drain regions in regions of the fin not covered by the mask or spacer electrically couple to the channel through the tip region. The channel mask is replaced with a gate stack.

Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.

Abstract: Solid-state assemblies including dielectric lining layers having localized charges are provided. Processes to form the solid-state assemblies also are provided. The solid-state assemblies can included in CMOS transistors, where first dielectric lining layers having localized charges of positive polarity can be adjacent to the PMOS member and a second dielectric lining layers having localized charges of positive polarity can be adjacent to an NMOS member. The first dielectric lining layers can be adjacent to a first gate electrode of the CMOS transistor, and the second dielectric lining can be adjacent to a second gate electrode of the CMOS transistor. The first dielectric lining layers and the second dielectric lining layers can improve, at least in part, the performance of the CMOS transistor by attracting mobile carriers into respective transport channels of the PMOS member and the NMOS member.