Abstract: Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal.

Abstract: In various embodiments, the disclosure describes transistors having non-vertical gates. In one embodiment, the non-vertical gates can have a curved or wide angle gate in order to reduce the electric field crowing on the drain side of the gate edge and/or portions having corners and thereby reduce leakage current in the transistor. In one embodiment, the non-vertical gate can be generated by one or more etching steps (for example, isotropic etching steps) of an underlying channel during the fabrication of a transistor having the non-vertical gate. In one embodiment, the non-vertical gate can be generated by one or more directional etching steps that may expose various facets having predetermined orientations of a source and/or drain associated with the transistor.

Abstract: Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract: Semiconductor devices including a subfin including a first III-V semiconductor alloy and a channel including a second III-V semiconductor alloy are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V semiconductor alloy is deposited on the substrate within the trench and the second III-V semiconductor alloy is epitaxially grown on the first III-V semiconductor alloy. In some embodiments, a conduction band offset between the first III-V semiconductor alloy and the second III-V semiconductor alloy is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.

Abstract: An apparatus is described. The apparatus includes a FINFET transistor. The FINFET transistor comprises a tapered subfin structure having a sidewall surface area that is large enough to induce aspect ratio trapping of lattice defects along sidewalls of the subfin structure so that the defects are substantially prevented from reaching said FINFET transistor's channel.

Abstract: Transistor devices may be formed having a buffer between an active channel and a substrate, wherein the active channel and a portion of the buffer form a gated region. The active channel may comprise a low band-gap material on a sub-structure, e.g. the buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electron mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure.

Abstract: Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.

Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.

Abstract: Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.

Abstract: A buffer layer is deposited on a substrate. A first III-V semiconductor layer is deposited on the buffer layer. A second III-V semiconductor layer is deposited on the first III-V semiconductor layer. The second III-V semiconductor layer comprises a channel portion and a source/drain portion. The first III-V semiconductor layer acts as an etch stop layer to etch a portion of the second III-V semiconductor layer to form the source/drain portion.

Abstract: Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

Abstract: Monolithic FETs including a channel region in a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a channel region, a semiconductor spacer of a semiconductor material with a band offset relative to the channel material is grown, for example on at least a drain end of the channel region to introduce at least one charge carrier-blocking band offset between the channel semiconductor and a drain region of a third III-V semiconductor material. In some N-type transistor embodiments, the carrier-blocking band offset is a conduction band offset of at least 0.1 eV. A wider band gap and/or a blocking conduction band offset may contribute to reduced gate induced drain leakage (GIDL). Source/drain regions couple electrically to the channel region through the semiconductor spacer, which may be substantially undoped (i.e. intrinsic) or doped.

Abstract: Disclosed herein are transistor amorphous interlayer arrangements, and related methods and devices. For example, in some embodiments, transistor amorphous interlayer arrangement may include a channel material and a transistor source/drain stack. The transistor source/drain stack may include a transistor electrode material configured to be a transistor source/drain contact, i.e. either a source contact or a drain contact of the transistor, and a doped amorphous semiconductor material disposed between the transistor electrode material and the channel material.

Abstract: Embodiments of the present disclosure describe semiconductor devices comprised of a semiconductor substrate with a metal oxide semiconductor field effect transistor having a channel including germanium or silicon-germanium, where a dielectric layer is coupled to the channel. The dielectric layer may include a metal oxide and at least one additional element, where the at least one additional element may increase a band gap of the dielectric layer. A gate electrode may be coupled to the dielectric layer. Other embodiments may be described and/or claimed.

Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.

Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A counter-doped portion of a III-V semiconductor material provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where it might otherwise behave as electrically active amphoteric contaminate in the III-V material. In some embodiments, counter-dopants (e.g., acceptor impurities) are introduced in-situ during epitaxial growth of a base portion of a sub-fin structure. With the counter-doped region limited to a base of the sub-fin structure, risk of the counter-dopant atoms thermally diffusing into an active region of a III-V transistor is mitigated.

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract: An embodiment includes a device comprising: a substrate; a dielectric layer on the substrate and including a trench; a first portion of the trench including a first material that comprises at least one of a group III-V material and a group IV material; and a second portion of the trench, located between the first portion and the substrate, which includes a second material and an upper region and a lower region; wherein: (a)(i) the second material in the upper region has fewer defects than the second material in the lower region, and (a)(ii) the first material is strained. Other embodiments are described herein.