Abstract: Some embodiments include apparatuses and methods having a node to receive ground potential, a first diode including an anode coupled to the node, a second diode including an anode coupled to the node, a first circuit to apply a voltage to a cathode of each of the first and second diodes to cause the first and second diodes to be in a forward-bias condition, and a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode. At least one of such the embodiments includes a temperature calculator to calculate a value of temperature based at least in part on the duty cycle of the signal.

Abstract: An apparatus is described having a reference voltage circuit. The reference voltage circuit includes a diode to receive first and second currents having first and second respective current densities, where, the first and second current densities are different and determined by circuitry that precisely controls the respective amount of time the first and second currents flow into the diode. The reference voltage circuit also comprises circuitry to form a reference voltage by combining first and second voltages generated from respective voltages of the diode that result from the first and second currents flowing through the diode.

Abstract: Some embodiments include apparatuses and methods having a node to receive ground potential, a first diode including an anode coupled to the node, a second diode including an anode coupled to the node, a first circuit to apply a voltage to a cathode of each of the first and second diodes to cause the first and second diodes to be in a forward-bias condition, and a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode. At least one of such the embodiments includes a temperature calculator to calculate a value of temperature based at least in part on the duty cycle of the signal.

Abstract: Embodiments of the present disclosure provide techniques and configurations for integrally determining a parameter (e.g., temperature) of a die of an integrated circuit. In one instance, the apparatus may comprise a die including a first (e.g., remote) area and a second (e.g., local) area disposed at a distance from the first area, and circuitry to determine a parameter associated with the remote area of the die. The circuitry may include: a first sensing device disposed in the remote area, to provide first readings associated with the parameter; a second sensing device disposed in the local area, to provide second readings associated with the parameter; and a control module coupled with the sensing devices and disposed in the local area, to facilitate a determination of the parameter based on the first and second readings provided by the first and second sensing devices. Other embodiments may be described and/or claimed.

Abstract: Described are apparatuses and methods for generating a temperature-stabilized reference voltage on a semiconductor chip. An apparatus may include a differential amplifier including a first input, a second input, and an output. The apparatus may further include a first bipolar junction transistor (BJT) coupled to the first input; a second BJT coupled to the second input; and beta compensation circuitry, coupled to the first BJT and the second BJT, to regulate a first collector current of the first BJT to be independent of a first current gain of the first BJT and a second collector current of the second BJT to be independent of a second current gain of the second BJT. Other embodiments may be described and/or claimed.

Abstract: Described is a current-mode thermal sensor apparatus which comprises: a first transistor with a gate terminal coupled to a first node; a second transistor with a gate terminal coupled to a second node; a first resistor coupled to the first and second nodes; a second resistor coupled to the first node and a supply node; and a diode coupled to the second node and the supply node.

Abstract: Described is a current-mode thermal sensor apparatus which comprises: a first transistor with a gate terminal coupled to a first node; a second transistor with a gate terminal coupled to a second node; a first resistor coupled to the first and second nodes; a second resistor coupled to the first node and a supply node; and a diode coupled to the second node and the supply node.

Abstract: Described are apparatuses and methods for generating a temperature-stabilized reference voltage on a semiconductor chip. An apparatus may include a differential amplifier including a first input, a second input, and an output. The apparatus may further include a first bipolar junction transistor (BJT) coupled to the first input; a second BJT coupled to the second input; and beta compensation circuitry, coupled to the first BJT and the second BJT, to regulate a first collector current of the first BJT to be independent of a first current gain of the first BJT and a second collector current of the second BJT to be independent of a second current gain of the second BJT. Other embodiments may be described and/or claimed.

Abstract: A circuit arrangement may include: a first bipolar transistor; a second bipolar transistor; wherein the circuit arrangement is configured to provide a first current flowing through the first bipolar transistor and a second current flowing through the second bipolar transistor; a resistor connected between a first input of the first bipolar transistor and a first input of the second bipolar transistor; a first circuit configured to provide a first current flowing through the resistor to a first input node of the first bipolar transistor, and a second circuit configured to provide a reference current to the first input node of the first bipolar transistor, wherein the first current and the reference current have different temperature dependencies.

Abstract: A circuit for generating a temperature-stabilized reference voltage on a semiconductor chip includes a differential amplifier having a first input, a second input and an output. The circuit further includes a CTAT circuit configured to generate a CTAT voltage at an output thereof. A first resistor is coupled between the output of the differential amplifier and the output of the CTAT circuit. Further, the first resistor is connected between the first input and the second input of the differential amplifier.

Abstract: A circuit for generating a temperature-stabilized reference voltage on a semiconductor chip includes a differential pair including a first and a second bipolar junction transistor. The circuit further includes a feedback circuit including an amplification stage and configured to control a current flowing through the first bipolar junction transistor and a current flowing through the second bipolar junction transistor. A first resistor is connected between an emitter of the first bipolar junction transistor and an emitter of the second bipolar junction transistor, thereby generating a PTAT voltage across the first resistor. Further, the circuit includes a current source forcing a partial current having a CTAT behavior through the first resistor.

Abstract: A circuit for generating a temperature-stabilized reference voltage on a semiconductor chip includes a differential amplifier having a first input, a second input and an output. The circuit further includes a CTAT circuit configured to generate a CTAT voltage at an output thereof. A first resistor is coupled between the output of the differential amplifier and the output of the CTAT circuit. Further, the first resistor is connected between the first input and the second input of the differential amplifier.

Abstract: A circuit arrangement may include: a first bipolar transistor; a second bipolar transistor; wherein the circuit arrangement is configured to provide a first current flowing through the first bipolar transistor and a second current flowing through the second bipolar transistor; a resistor connected between a first input of the first bipolar transistor and a first input of the second bipolar transistor; a first circuit configured to provide a first current flowing through the resistor to a first input node of the first bipolar transistor, and a second circuit configured to provide a reference current to the first input node of the first bipolar transistor, wherein the first current and the reference current have different temperature dependencies.

Abstract: A circuit for generating a temperature-stabilized reference voltage on a semiconductor chip includes a differential pair including a first and a second bipolar junction transistor. The circuit further includes a feedback circuit including an amplification stage and configured to control a current flowing through the first bipolar junction transistor and a current flowing through the second bipolar junction transistor. A first resistor is connected between an emitter of the first bipolar junction transistor and an emitter of the second bipolar junction transistor, thereby generating a PTAT voltage across the first resistor. Further, the circuit includes a current source forcing a partial current having a CTAT behavior through the first resistor.

Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.

Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.

Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.

Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.

Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.

Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.