Patents by Inventor Matthias Eberlein
Matthias Eberlein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170074924Abstract: Embodiments of the present disclosure provide techniques and configurations for integrally determining a parameter (e.g., temperature) of a die of an integrated circuit. In one instance, the apparatus may comprise a die including a first (e.g., remote) area and a second (e.g., local) area disposed at a distance from the first area, and circuitry to determine a parameter associated with the remote area of the die. The circuitry may include: a first sensing device disposed in the remote area, to provide first readings associated with the parameter; a second sensing device disposed in the local area, to provide second readings associated with the parameter; and a control module coupled with the sensing devices and disposed in the local area, to facilitate a determination of the parameter based on the first and second readings provided by the first and second sensing devices. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: Cho-Ying Lu, Matthias Eberlein, Hyung-Jin Lee
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Patent number: 9568929Abstract: Described are apparatuses and methods for generating a temperature-stabilized reference voltage on a semiconductor chip. An apparatus may include a differential amplifier including a first input, a second input, and an output. The apparatus may further include a first bipolar junction transistor (BJT) coupled to the first input; a second BJT coupled to the second input; and beta compensation circuitry, coupled to the first BJT and the second BJT, to regulate a first collector current of the first BJT to be independent of a first current gain of the first BJT and a second collector current of the second BJT to be independent of a second current gain of the second BJT. Other embodiments may be described and/or claimed.Type: GrantFiled: July 28, 2014Date of Patent: February 14, 2017Assignee: INTEL CORPORATIONInventor: Matthias Eberlein
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Patent number: 9557226Abstract: Described is a current-mode thermal sensor apparatus which comprises: a first transistor with a gate terminal coupled to a first node; a second transistor with a gate terminal coupled to a second node; a first resistor coupled to the first and second nodes; a second resistor coupled to the first node and a supply node; and a diode coupled to the second node and the supply node.Type: GrantFiled: July 22, 2013Date of Patent: January 31, 2017Assignee: Intel CorporationInventor: Matthias Eberlein
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Publication number: 20160138978Abstract: Described is a current-mode thermal sensor apparatus which comprises: a first transistor with a gate terminal coupled to a first node; a second transistor with a gate terminal coupled to a second node; a first resistor coupled to the first and second nodes; a second resistor coupled to the first node and a supply node; and a diode coupled to the second node and the supply node.Type: ApplicationFiled: July 22, 2013Publication date: May 19, 2016Inventor: Matthias EBERLEIN
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Publication number: 20160026198Abstract: Described are apparatuses and methods for generating a temperature-stabilized reference voltage on a semiconductor chip. An apparatus may include a differential amplifier including a first input, a second input, and an output. The apparatus may further include a first bipolar junction transistor (BJT) coupled to the first input; a second BJT coupled to the second input; and beta compensation circuitry, coupled to the first BJT and the second BJT, to regulate a first collector current of the first BJT to be independent of a first current gain of the first BJT and a second collector current of the second BJT to be independent of a second current gain of the second BJT. Other embodiments may be described and/or claimed.Type: ApplicationFiled: July 28, 2014Publication date: January 28, 2016Inventor: Matthias Eberlein
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Patent number: 9240775Abstract: A circuit arrangement may include: a first bipolar transistor; a second bipolar transistor; wherein the circuit arrangement is configured to provide a first current flowing through the first bipolar transistor and a second current flowing through the second bipolar transistor; a resistor connected between a first input of the first bipolar transistor and a first input of the second bipolar transistor; a first circuit configured to provide a first current flowing through the resistor to a first input node of the first bipolar transistor, and a second circuit configured to provide a reference current to the first input node of the first bipolar transistor, wherein the first current and the reference current have different temperature dependencies.Type: GrantFiled: March 12, 2013Date of Patent: January 19, 2016Assignee: INTEL DEUTSCHLAND GMBHInventor: Matthias Eberlein
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Patent number: 9122290Abstract: A circuit for generating a temperature-stabilized reference voltage on a semiconductor chip includes a differential amplifier having a first input, a second input and an output. The circuit further includes a CTAT circuit configured to generate a CTAT voltage at an output thereof. A first resistor is coupled between the output of the differential amplifier and the output of the CTAT circuit. Further, the first resistor is connected between the first input and the second input of the differential amplifier.Type: GrantFiled: March 15, 2013Date of Patent: September 1, 2015Assignee: Intel Deutschland GmbHInventor: Matthias Eberlein
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Publication number: 20140266413Abstract: A circuit for generating a temperature-stabilized reference voltage on a semiconductor chip includes a differential pair including a first and a second bipolar junction transistor. The circuit further includes a feedback circuit including an amplification stage and configured to control a current flowing through the first bipolar junction transistor and a current flowing through the second bipolar junction transistor. A first resistor is connected between an emitter of the first bipolar junction transistor and an emitter of the second bipolar junction transistor, thereby generating a PTAT voltage across the first resistor. Further, the circuit includes a current source forcing a partial current having a CTAT behavior through the first resistor.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: Intel Mobile Communications GmbHInventor: Matthias Eberlein
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Publication number: 20140269834Abstract: A circuit arrangement may include: a first bipolar transistor; a second bipolar transistor; wherein the circuit arrangement is configured to provide a first current flowing through the first bipolar transistor and a second current flowing through the second bipolar transistor; a resistor connected between a first input of the first bipolar transistor and a first input of the second bipolar transistor; a first circuit configured to provide a first current flowing through the resistor to a first input node of the first bipolar transistor, and a second circuit configured to provide a reference current to the first input node of the first bipolar transistor, wherein the first current and the reference current have different temperature dependencies.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Inventor: Matthias Eberlein
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Publication number: 20140266139Abstract: A circuit for generating a temperature-stabilized reference voltage on a semiconductor chip includes a differential amplifier having a first input, a second input and an output. The circuit further includes a CTAT circuit configured to generate a CTAT voltage at an output thereof. A first resistor is coupled between the output of the differential amplifier and the output of the CTAT circuit. Further, the first resistor is connected between the first input and the second input of the differential amplifier.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventor: Matthias Eberlein
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Patent number: 8816756Abstract: A circuit for generating a temperature-stabilized reference voltage on a semiconductor chip includes a differential pair including a first and a second bipolar junction transistor. The circuit further includes a feedback circuit including an amplification stage and configured to control a current flowing through the first bipolar junction transistor and a current flowing through the second bipolar junction transistor. A first resistor is connected between an emitter of the first bipolar junction transistor and an emitter of the second bipolar junction transistor, thereby generating a PTAT voltage across the first resistor. Further, the circuit includes a current source forcing a partial current having a CTAT behavior through the first resistor.Type: GrantFiled: March 13, 2013Date of Patent: August 26, 2014Assignee: Intel Mobile Communications GmbHInventor: Matthias Eberlein
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Patent number: 7482790Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.Type: GrantFiled: March 19, 2007Date of Patent: January 27, 2009Assignee: Dialog Semiconductor GmbHInventor: Matthias Eberlein
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Patent number: 7477044Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.Type: GrantFiled: March 19, 2007Date of Patent: January 13, 2009Assignee: Dialog Semiconductor GmbHInventor: Matthias Eberlein
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Patent number: 7477043Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.Type: GrantFiled: March 19, 2007Date of Patent: January 13, 2009Assignee: Dialog Semiconductor GmbHInventor: Matthias Eberlein
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Patent number: 7477046Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.Type: GrantFiled: March 19, 2007Date of Patent: January 13, 2009Assignee: Dialog Semiconductor GmbHInventor: Matthias Eberlein
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Publication number: 20070188156Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.Type: ApplicationFiled: March 19, 2007Publication date: August 16, 2007Inventor: Matthias Eberlein
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Publication number: 20070170901Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.Type: ApplicationFiled: March 19, 2007Publication date: July 26, 2007Inventor: Matthias Eberlein
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Publication number: 20070164716Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.Type: ApplicationFiled: March 19, 2007Publication date: July 19, 2007Inventor: Matthias Eberlein
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Publication number: 20070159144Abstract: Circuits and methods to provide an LDO output stage implemented with low-voltage devices. and still allowing higher voltage levels have been achieved. The output stage has been built using two low voltage MOS devices in series. During the time the regulator is in active mode the second MOS device acts as a small resistor in series to the pass device. During power down this second device actively protects the MOS pass device and itself from high voltage stress levels. This is achieved by a robust regulating mechanism that compensates leakage currents. These leakage currents normally determine the different potentials of the output stage during power down. Although the second transistor presents a resistive obstacle during active mode the total chip area required is smaller compared to a single pass device tolerating e.g. 5 Volts.Type: ApplicationFiled: March 19, 2007Publication date: July 12, 2007Inventor: Matthias Eberlein
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Patent number: 7236015Abstract: A method for dynamically adapting the biasing current for a fast switching CMOS comparator is achieved. The difference of the two input signals of said comparator controls the comparator's biasing current, where the biasing current is high only when the difference is low and the comparator's switching is likely to happen and where the biasing current is kept low at other times. In a current mirroring circuit, the voltage difference at the comparator inputs controls the mirroring ratio. The biasing current reaches its maximum when the input voltage difference approaches zero. Once the input voltage difference crosses zero and continues to change in the same direction as before, that is after the polarity of the voltage difference changed, the control mechanism alternates the connection of the comparator input signals to the current controlling elements, in order to now reduce the current with a further increase of the voltage difference.Type: GrantFiled: April 17, 2002Date of Patent: June 26, 2007Assignee: Dialog Semiconductor GmbHInventor: Matthias Eberlein