Abstract: In at least one embodiment, the optoelectronic component comprises an optoelectronic semiconductor chip with an emission side and a rear side opposite the emission side. Furthermore, the component comprises a housing body with a top side and an underside opposite the top side, and a metal layer on the top side of the housing body. During proper operation, the semiconductor chip emits primary electromagnetic radiation via the emission side. The semiconductor chip is embedded in the housing body and laterally surrounded by the housing body. The emission side is on the rear side and the top side is downstream of the underside along a main emission direction of the semiconductor chip. The metal layer is at least partially reflecting or absorbing radiation generated by the optoelectronic component.

Abstract: An optoelectronic semiconductor chip, a method for manufacturing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment an optoelectronic semiconductor chip includes a semiconductor layer sequence having an emission side, the emission side comprising a plurality of emission fields, partition walls on the emission side in a region between two adjacent emission fields and a conversion element on one or more emission fields, wherein the conversion element includes a matrix material with first phosphor particles incorporated therein, wherein the first phosphor particles are sedimented in the matrix material such that a mass fraction of the first phosphor particles is greater in a lower region of the conversion element facing the semiconductor layer sequence than in a remaining region of the conversion element, and wherein the partition walls are attached to the emission side without any additional connectors.

Abstract: A light source includes a plurality of semiconductor components, wherein a semiconductor component includes a plurality of light-emitting diodes, the diodes are arranged in a predefined grid in at least one column in or on the semiconductor component, and a control circuit that drives the individual diodes is arranged on the semiconductor component.

Abstract: An optoelectronic component includes a layer configured to generate an electromagnetic radiation including a first wavelength; a second layer including a conversion material and a scattering material, wherein the conversion material is configured to shift the first wavelength of the electromagnetic radiation to a second wavelength, and the scattering material is configured to scatter the first wavelength to a greater extent than the second wavelength.

Abstract: A light source includes a plurality of semiconductor components, wherein a semiconductor component includes a plurality of light-emitting diodes, the diodes are arranged in a predefined grid in at least one column in or on the semiconductor component, and a control circuit that drives the individual diodes is arranged on the semiconductor component.

Abstract: The invention concerns a semiconductor chip (100) with a semiconductor body (2) having a semiconductor layer sequence, and with a substrate body (4) and at least one upper side contact (8). In projection the semiconductor chip (100) has a shape which deviates from a rectangular shape. The invention also concerns a method of separating a composite into a plurality of semiconductor chips (100) along a separation pattern (15) with the steps enabling a plurality of semiconductor chips according to the invention to be produced.

Abstract: An optoelectronic component includes a leadframe, a molded body connected to the leadframe, and an optoelectronic semiconductor chip arranged on the leadframe, wherein the leadframe includes an alignment opening, and wherein the molded body includes a recess via which the leadframe is exposed in the area of the alignment opening.

Abstract: An optoelectronic component includes a leadframe, a molded body connected to the leadframe, and an optoelectronic semiconductor chip arranged on the leadframe, wherein the leadframe includes an alignment opening, and wherein the molded body includes a recess via which the leadframe is exposed in the area of the alignment opening.

Abstract: The invention concerns a semiconductor chip (100) with a semiconductor body (2) having a semiconductor layer sequence, and with a substrate body (4) and at least one upper side contact (8). In projection the semiconductor chip (100) has a shape which deviates from a rectangular shape. The invention also concerns a method of separating a composite into a plurality of semiconductor chips (100) along a separation pattern (15) with the steps enabling a plurality of semiconductor chips according to the invention to be produced.

Abstract: The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

Abstract: The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

Abstract: The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

Abstract: SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material.

Abstract: The present disclosure provides for semiconductor device structures and methods for forming semiconductor device structures, wherein a field-inducing structure is provided lower than an active portion of a fin along a height dimension of that fin, the height dimension extending in parallel to a normal direction of a semiconductor substrate surface in which the fin is formed. The field-inducing structure hereby implements a permanent field effect below the active portion. The active portion of the fin is to be understood as a portion of the fin covered by a gate dielectric.

Abstract: Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.

Abstract: A cleaning device (1) for a lens (2) of a headlight of a motor vehicle has two telescoping tubes (6, 7), the outer tube (6) holding a spray nozzle (9). The outer tube (6) is also surrounded by a protective tube (8) to be fixed in the motor vehicle. When the outer tube (6) is pulled out (9), the spray nozzle is displaced over the lens (2). The connections of the tubes (6, 7) are reliably protected from dirt accumulation.

Abstract: A semiconductor structure includes a resistor. The resistor includes a semiconductor region, a dielectric layer, a first electrical connection and a second electrical connection. The dielectric layer is provided on the semiconductor region and includes a high-k material having a greater dielectric constant than silicon dioxide. The dielectric layer includes a species creating fixed charges. A first electrical connection is provided at a first end of the semiconductor region and a second electrical connection is provided at a second end of the semiconductor region.

Abstract: Methods are provided for forming semiconductor devices. One method includes etching trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. Dummy gate structures are formed, which includes a first dummy gate structure, that overlie and are transverse to the fins. A back fill material is filled between the dummy gate structures. The first dummy gate structure and an upper portion of the insulating material are removed to expose an active fins portion of the fins. The active fins portion is dimensionally modified to form an altered active fins portion. A high-k dielectric material and a work function determining gate electrode material are deposited overlying the altered active fins portion.

Abstract: Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.

Abstract: SRAM ICs and methods for their fabrication are provided. One method includes depositing photoresist on a first oxide layer overlying a silicon substrate, forming a pattern of locations, using said photoresist, for the formation of two inverters, each having a pull up transistor, a pull down transistor, and a pass gate transistor on said oxide layer. The method involves anisotropically etching U-shaped channels in the oxide layer corresponding to pattern, and thereafter isotropically etching U-shaped channels in the silicon layer to form saddle-shaped fins in the silicon. A second oxide layer is deposited over the saddle-shaped fins, and a first metal layer is deposited over the second oxide layer. A contact metal layer is formed over the first metal layer and planarized to form local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors.