Abstract: A method and an apparatus for voltage level shifting are described. A voltage level shifter includes two level shifting circuits and a differential amplifier. The differential amplifier forms a feedback loop with one level shifting circuit. The feedback loop controls the level shifting operation of both level shifting circuits. The differential amplifier can operate to provide a control signal that causes a level-shifted signal in the feedback loop to match a target signal. The two level shifting circuits can perform their level shifting operation based on the control signal.

Abstract: In a circuit having a runaway detector coupled to a phase-locked loop (PLL), the PLL may include a loop filter to receive a control voltage within the PLL and provide a filtered control voltage and a voltage-controlled oscillator to receive the filtered control voltage and provide an output clock signal. The runaway detector may provide a control signal for adjusting the filtered control voltage in response to a predetermined PLL condition. The runaway detector may include a comparator to receive a first and second input voltages, where the second input voltage is based on the output clock signal. When the predetermined PLL condition exists, the runaway detector may be active to adjust the filtered control voltage k thereby enabling the PLL to return to a lock condition.

Abstract: In a method for dividing a frequency of a clock signal, a first frequency divided signal is generated based on a clock signal. Rising edges in the first frequency divided signal are detected. Alternatively, falling edges in the first frequency divided signal are detected. An edge detection signal that includes a pulse for each detected edge is generated. A second frequency divided signal is generated based on the edge detection signal.

Abstract: A device including an input to receive a differential waveform pair from a transmission line, the differential waveform pair including a first waveform and a second waveform. The device also includes a repeater to generate a refreshed first output waveform and a refreshed second output waveform. The refreshed first output waveform is substantially similar to an inverted copy of the first waveform and is generated after a signal transition of the first waveform and after a complementary signal transition of the second waveform. The refreshed second output waveform is substantially similar to an inverted copy of the second waveform and is generated substantially simultaneously with generation of the first output waveform.

Abstract: One disclosed method involves suppressing ringing on a voltage regulator output by using a load compensator to monitor the output of the voltage regulator. If an output voltage is detected that is greater than a first predefined level, the output voltage is driven lower, and if an output voltage is detected that is less than a second predefined level, the output voltage is driven higher.

Abstract: One disclosed method includes controlling an output voltage to track a reference voltage by using a feedback loop to monitor an output duty cycle and to maintain an output voltage that is substantially constant relative to the reference voltage.

Abstract: A speed-locked loop (SLL) circuit to automatically determine overall chip speed, which is a function of the combination of supply voltage, temperature, and processing parameters, and to output the speed information in digital form to speed-compensating circuits in order to significantly reduce their sensitivity to operating conditions. Through negative feedback, a digitally controlled ring oscillator (DCO) is forced to lock at an oscillation frequency close to that specified by a six-bit speed constant input. A three-bit control bus varies the DCO oscillation frequency under digital control until the SLL achieves lock. When the SLL has achieved lock it latches the DCO control bus and outputs it as the speed information. The speed constant input may be varied under software control in order to determine the speed constant value that optimizes performance of speed-compensating circuits under SLL control.

Abstract: A speed-locked loop (SLL) circuit to automatically determine overall chip speed, which is a function of the combination of supply voltage, temperature, and processing parameters, and to output the speed information in digital form to speed-compensating circuits in order to significantly reduce their sensitivity to operating conditions. Through negative feedback, a digitally controlled ring oscillator (DCO) is forced to lock at an oscillation frequency close to that specified by a six-bit speed constant input. A three-bit control bus varies the DCO oscillation frequency under digital control until the SLL achieves lock. When the SLL has achieved lock it latches the DCO control bus and outputs it as the speed information. The speed constant input may be varied under software control in order to determine the speed constant value that optimizes performance of speed-compensating circuits under SLL control.

Abstract: A speed-locked loop (SLL) circuit to automatically determine overall chip speed, which is a function of the combination of supply voltage, temperature, and processing parameters, and to output the speed information in digital form to speed-compensating circuits in order to significantly reduce their sensitivity to operating conditions. Through negative feedback, a digitally controlled ring oscillator (DCO) is forced to lock at an oscillation frequency close to that specified by a six-bit speed constant input. A three-bit control bus varies the DCO oscillation frequency under digital control until the SLL achieves lock. When the SLL has achieved lock it latches the DCO control bus and outputs it as the speed information. The speed constant input may be varied under software control in order to determine the speed constant value that optimizes performance of speed-compensating circuits under SLL control.

Abstract: A circuit to divide down the frequency of a clock signal, where embodiment circuits comprise a set-reset flip-flop feeding its output to a shift register, and combinational logic to provide feedback from the shift register to the set input port, reset input port, or both set and reset input ports of the set-reset flip-flop. The set-reset flip-flop and shift register are clocked by the clock signal. The output signal of the circuit may be taken at any output port of the shift register or the set-reset flip-flop. In one embodiment, the state of the shift register is represented by the set of Boolean values Q<i>, i=1, 2, . . . , N?1, and the combinational logic provides to the set input port of the set-reset flip-flop the Boolean value {Q#<M?1><Q#<M?2>. . .

Abstract: A digital phase detector and jitter filter. For one aspect, a digital phase detector receives first and second input signals and provides at least one of a digital LEAD and LAG output signal. Multiple inputs of a digital filter are collectively coupled to receive the digital output signal from the digital phase detector. The digital filter provides a multi-bit digital phase error output signal to indicate a phase error between the first and second signals. Phase-lock is indicated when the phase error output signal indicates a value substantially in the center of the range of possible integer combinations that may be provided by the multi-bit output signal.

Abstract: A device including an input to receive a differential waveform pair from a transmission line, the differential waveform pair including a first waveform and a second waveform. The device also includes a repeater to generate a refreshed first output waveform and a refreshed second output waveform. The refreshed first output waveform is substantially similar to an inverted copy of the first waveform and is generated after a signal transition of the first waveform and after a complementary signal transition of the second waveform. The refreshed second output waveform is substantially similar to an inverted copy of the second waveform and is generated substantially simultaneously with generation of the first output waveform.

Abstract: A speed-locked loop (SLL) circuit to automatically determine overall chip speed, which is a function of the combination of supply voltage, temperature, and processing parameters, and to output the speed information in digital form to speed-compensating circuits in order to significantly reduce their sensitivity to operating conditions. Through negative feedback, a digitally controlled ring oscillator (DCO) is forced to lock at an oscillation frequency close to that specified by a six-bit speed constant input. A three-bit control bus varies the DCO oscillation frequency under digital control until the SLL achieves lock. When the SLL has achieved lock it latches the DCO control bus and outputs it as the speed information. The speed constant input may be varied under software control in order to determine the speed constant value that optimizes performance of speed-compensating circuits under SLL control.

Abstract: A speed-locked loop (SLL) circuit to automatically determine overall chip speed, which is a function of the combination of supply voltage, temperature, and processing parameters, and to output the speed information in digital form to speed-compensating circuits in order to significantly reduce their sensitivity to operating conditions. Through negative feedback, a digitally controlled ring oscillator (DCO) is forced to lock at an oscillation frequency close to that specified by a six-bit speed constant input. A three-bit control bus varies the DCO oscillation frequency under digital control until the SLL achieves lock. When the SLL has achieved lock it latches the DCO control bus and outputs it as the speed information. The speed constant input may be varied under software control in order to determine the speed constant value that optimizes performance of speed-compensating circuits under SLL control.

Abstract: In one embodiment, N transmission gates having N outputs transfer one of N pattern inputs to a first output based on an active signal from N select signals. The N outputs are connected together to form the first output and has an output capacitance. An amplifier circuit having a gain is coupled to the N transmission gates at the first output to reduce the output capacitance by an amount approximately equal to the gain. The amplifier circuit generates an output signal.

Abstract: In one embodiment, N transmission gates having N outputs transfer one of N pattern inputs to a first output based on an active signal from N select signals. The N outputs are connected together to form the first output and has an output capacitance. An amplifier circuit having a gain is coupled to the N transmission gates at the first output to reduce the output capacitance by an amount approximately equal to the gain. The amplifier circuit generates an output signal.

Abstract: Apparatus including a virtual zener diode circuit including a complementary metal oxide semiconductor (CMOS) circuit that mimics an operation of a true zener diode.

Abstract: A boosted high gain, very wide common mode range, self-biased operational amplifier comprising complementary differential transistor pairs biased by biasing transistors and current mirrors, and comprising two amplifiers, each connected to bias an output cascode transistor so as to provide a very high amplifier output impedance, wherein the biasing transistors and current mirrors are all self-biased via negative feedback.

Abstract: A boosted high gain, very wide common mode range, self-biased operational amplifier comprising complementary differential transistor pairs biased by biasing transistors and current mirrors, and comprising two amplifiers, each connected to bias an output cascode transistor so as to provide a very high amplifier output impedance, wherein the biasing transistors and current mirrors are all self-biased via negative feedback.

Abstract: A high gain, very wide common mode range, self-biased operational amplifier comprising complementary differential transistor pairs biased by biasing transistors and current mirrors, and further comprising cascode transistors to provide a high amplifier output impedance, wherein the biasing transistors, current mirrors, and cascode transistors are all self-biased via negative feedback.