Abstract: A method and an apparatus for reducing baseline wander in a differential signal. In one embodiment, the differential signal is carried in first and second signal lines. If negative baseline wander is detected in the differential signal, a first pair of current sources is activated. One of the first pair of current sources thereby sources current into the first signal line and the other one of the first pair of current sources thereby sinks current from the second signal line as a result until the negative baseline wander is reduced to a level approximately equal to a preset threshold value. If positive baseline wander is detected in the differential signal, a second pair of current sources is activated.

Abstract: An adaptive equalizer is implemented using digital feedback control and using jitter as the adjustment criteria. An adjustable transfer function is implemented to equalize an input signal to enhance the frequency response of the associated system. Jitter is determined for the filtered signal, and the frequency response of the transfer function is varied accordingly by applying a digital adjustment signal to the transfer function structure (for example, a lead-lag filter). The adaptive equalizer can thereby adapt to various transmission medium lengths and signal degradation levels.

Abstract: A method and an apparatus for detecting differential threshold levels of a differential signal being carried in first and second lines while compensating for baseline wander. In one embodiment, first and second single-ended signals and a common mode signal are generated in response to the first and second lines. First and second peak signals are then generated in response to the first and second single-ended signals and the common mode signal. Finally, first and second threshold signals are generated which are compared with the first and second single-ended signals to generate first and second output signals indicating first and second differential threshold levels.

Abstract: An integrated circuit utilizing a symmetric phase detection circuit for detecting a phase relationship between a reference clock signal and a delayed clock signal. The integrated circuit described herein features a control block circuit coupled to receive the reference clock signal and an enable check signal. The control block circuit generates an enable signal which provides the present invention with the ability to detect the phase difference between signals having the same frequency or signals that differ in frequency by a rational factor. The control block circuit generates the enable signal in response to the enable check signal and the reference clock signal. The enable signal, the reference clock signal, and the delayed clock signal are coupled to the phase detection circuit. In response to the enable signal, the phase detection circuit then determines the phase relationship between the reference clock signal and delayed clock signal.

Abstract: A method and an apparatus for providing an adjustable floating capacitance between a first node and a second node in an integrated circuit. First and second transistors having commonly coupled gates are coupled between the input and output nodes of a digitally-adjustable floating MOS capacitor. The source and drain of the first transistor are coupled to the input node, while the source and drain of the second transistor are coupled to the output node. A switch responsive to an enable signal is coupled to the gates of the first and second transistors. In response to the enable signal, the switch alternatively couples the gates of the first and second transistors to either a first potential or a second potential. When the gates of the first and second transistors are coupled to the first potential, a first capacitance is realized between the input and output nodes.

Abstract: An integrated circuit for selectively providing delay to a waveform carried on a signal line. With the present invention, a waveform is carried by a signal line to which a digitally-controlled capacitive load is coupled. A digital enable line is directly coupled to the capacitive load which either activates or deactivates the capacitive load. When the enable line is in the active state, the capacitive load is activated and the load therefore has maximum capacitance. Accordingly, the delay of the waveform carried on the signal line is also maximized. When the enable line is in the inactive state, the capacitive load has minimal capacitance and the delay of the signal being carried on the signal line is therefore minimized.

Abstract: A transformer including two half capacitive transformers operating in antiphase. Each half capacitive transformer steps an input voltage down during one phase of a clock signal. Each half capacitive transformer uses a number of capacitors and switching circuitry controlled by a clock signal. According to whether the clock signal is active or inactive, the switching circuitry places the half capacitive transformer in one of two configurations. In a first embodiment, in one configuration the capacitors are coupled in parallel between the input voltage and the output port, while in the other configuration, the capacitors are coupled in series between the output port and ground. In an alternative embodiment of the half capacitive transformer, in one configuration the capacitors are coupled in series between the input voltage and the output port while in the other configuration the capacitors are coupled in parallel between the output port and ground.

Abstract: An integrated circuit utilizing a symmetric phase detection circuit for detecting a phase relationship between a reference clock signal and a delayed clock signal. The integrated circuit described herein features a control block circuit coupled to receive the reference clock signal and an enable check signal. The control block circuit generates an enable signal which provides the present invention with the ability to detect the phase difference between signals having the same frequency or signals that differ in frequency by a rational factor. The control block circuit generates the enable signal in response to the enable check signal and the reference clock signal. The enable signal, the reference clock signal, and the delayed clock signal are coupled to the phase detection circuit. In response to the enable signal, the phase detection circuit then determines the phase relationship between the reference clock signal and delayed clock signal.

Abstract: An improved high precision synchronous delay line featuring propagation control circuitry in the voltage controlled delay line removing skew between a pair of propagated waveforms. A pair of waveforms are received by the voltage controlled delay line of the synchronous delay line. The voltage controlled delay line features propagation control circuitry which couples together the propagation of the pair of waveforms through the present invention. If a transition from one level to another level occurs on any one of the received pair of waveforms, the propagation control circuitry prevents the transition from propagating until a corresponding transition occurs on the other one of the pair of waveforms. As a result, any skew that is created between the pair of waveforms, for any reason, is removed by the propagation control circuitry. With the skew removed, the presently improved synchronous delay line features increased precision and provides for greater resolution.

Abstract: A shifter circuit of a digital filter circuit for providing an adjustable correction coefficient (.beta.) for the digital filter is described. The shifter circuit includes a first shifter for providing a first shift amount (S.sub.1) to an input signal, and a second shifter for providing a second shift amount (S.sub.2) to the input signal. Logic circuitry is provided in the shifter circuit that is coupled to the first and second shifters for receiving outputs of the first and second shifters under control of a control signal to generate an output signal of the shifter circuit with the adjustable correction coefficient (.beta.) such that digital filter has an adjustable bandwidth (BW) that is adjusted at a fine and substantially equal bandwidth increment. The adjustable correction coefficient (.beta.)is selectively derived from a combination of 2.sup.-S1 and 2.sup.-S2 such that the adjustable bandwidth (BW) is obtained from the equation: BW=-In(1-.beta.)/2.pi.T.sub.P.

Abstract: A reset discrimination circuit for identifying the completion of power-up via a valid deassertion of an external reset signal is described. When power-up is complete the reset discrimination circuit brings a function enable signal active, which initially powered up in the inactive state. The reset discrimination circuit includes a synchronous edge detector, a high counter, and a low counter. The synchronous edge detector detects the active state of the external reset signal and generates a first reset signal, which resets the high counter. After counting M clock pulses during the active state of the external reset signal the first counter enables the low counter. The low counter counts N clock pulses during the inactive state of the external reset signal to identify its valid deassertion. A method of identifying the completion of power-up by identifying the valid deassertion of an external reset signal is also described.

Abstract: A station of a ring network includes (1) a circuit for generating a configuration signal for connecting the station into the network and (2) a load circuit coupled to the first node and ground for receiving a DC component of the configuration signal. The DC component of the configuration signal is transparent with respect to data transmission of the network. A decoupling capacitor is coupled to the first node and ground for bypassing an AC component of the configuration signal at the first node to ground such that only the DC component of the configuration signal is applied to the load circuit. The circuit for generating the configuration signal includes (1) a first switch coupled to a power supply and a second node and (2) a capacitor coupled to the second node and ground. A second switch is provided in the circuit that is connected between the first and second nodes.

Abstract: Circuitry for overlapping a write access of a read-modify-write of a first bit with a subsequent read access of a second bit is described. The circuitry includes a latching circuit and a modify-write circuit. The latching circuit latches the active state of a select signal, which is used to select the SRAM cell storing the first bit during read and write accesses. The modify-write circuit modifies the first bit during the precharge preceding a read access of the second bit provided that it receives an active update write enable signal and an active signal from the latching circuit. Also described is a method of overlapping a read-modify-write cycle of a first SRAM bit with a subsequent read access of a second SRAM bit. The method begins by reading the first SRAM bit. Next, the second SRAM bit is precharged by bringing a precharge signal active. While the precharge signal is active the first SRAM bit is modified. Finally, the second SRAM bit is read after the precharge signal goes inactive.

Abstract: A synchronous delay line (SDL) for generating delayed signals synchronized with a clock signal is described. The present SDL includes a phase generator and a plurality of serially coupled voltage controlled delay elements. The phase generator takes the clock signal and generates a first trigger signal and a second trigger signal, which are substantially deskewed with respect to each other. Each of the delay elements receives two trigger inputs and outputs a delayed signal and two trigger outputs. The first and second trigger signals are coupled to one of the delay elements as trigger inputs. Each transition of the first and second trigger signals triggers the propagation of two waves through the delay line. The present SDL has a minimum tap-to-tap delay of only one inverter delay, versus a minimum tap-to-tap delay of two NAND gates in prior SDLs. Thus, the present SDL provides for double the number of output taps, and hence, double the resolution as compared to prior SDLs.

Abstract: An edge-sensitive pulse generator generating an output pulse having an arbitrary start time and an arbitrary stop time is described. The pulse generator includes a multiplexor whose output is selected by control signals. Inputs to the multiplexor include a start signal having a leading edge representative of said arbitrary start time and a trailing edge, and a stop signal having a leading edge representative of said arbitrary stop time and a trailing edge. The pulse generator also includes control logic for generating the control signals from the start signal and the stop signal. The control signals select the start signal as the multiplexor output after the trailing edge of the start signal and deselect the start signal as the mutiplexor output after the leading edge of said start signal. The control signals also select the stop signal as the multiplexor output after the trailing edge of the stop signal and select the stop signal as the multiplexor output after the leading edge of the stop signal.

Abstract: An integrated circuit for recovering the clock and data information from phase-encoded serial data. The circuit includes a synchronous delay line coupled to a waveform digitizer and a waveform synthesizer. The waveform digitizer receives and converts the phase-encoded data into a string of bits whose value represent the logic levels of an encoded data at T.sub.p /N intervals where T.sub.p is the reference clock period and N is the resolution of the waveform digitizer. The encoded data may be one of several phase-encoded serial data such as Manchester coding. The digitized output from the waveform digitizer is input to a transition detector, where the locations of the transitions (bit-boundary transitions and bit-center transitions) of the digitized encoded data are extracted. An AND stage comprising N AND gates is coupled to the waveform digitizer and the waveform synthesizer for masking out the bit-boundary transitions and passes the bit-center transitions.

Abstract: An integrated circuit apparatus for changing the phase relationship between at least one clock-phase output and a reference clock is disclosed. The sequence control apparatus is coupled to a waveform synthesizer apparatus producing at least one clock-phase output. The clock-phase output from the waveform synthesizer is looped back to a skew control apparatus. The deskew control apparatus measures the skew between the falling edge of the clock-phase output and the rising edge of the reference clock and generates a control signal to a shifter. The shifter deskews the clock-phase output automatically with respect to the reference clock by shifting an input pattern to a digital-to-time domain converter (DTC). A sampling window circuit in the deskew control apparatus is coupled to the shifter for reducing the skew between the reference clock and the clock-phase output to a small, well-defined amount.

Abstract: A synchronous delay line with quadrature clock phases provides for an improved output from the taps of a delay line. The delay line is comprised of a phase generator, a plurality of voltage controlled delay stages arranged serially, wherein the last VCD stage is coupled to a sample-and-hold circuit for providing an analog control voltage for controlling the delay. The phase generator generates in-phase clock signals to the interior delay stages, but provides quadrature clock phases to the delay stages at the extremities of the delay line. The quadrature clock phases provide for the low and high times of the tap outputs near the extremities of the synchronous delay line to be sufficiently long in duration for use in MOS circuits.

Abstract: An integrated circuit apparatus for performing digital synthesis of regular waveforms having transitions at arbitrary points in time is disclosed. A reference clock signal is provided as input to a synchronous delay line apparatus, producing a plurality of taps. The taps signal provides N inputs to a digital-to-time domain converter (DTC), where N is the resolution of the synthesized waveform, said DTC apparatus further receiving inputs from a pattern generator apparatus over a shifter apparatus and a pattern register apparatus. The DTC apparatus combines the taps signal and the input from said pattern register to produce a synthesized waveform. In the presently preferred embodiment, the DTC apparatus comprises a plurality of pairs of N-type and P-type devices connected as transmission gates. When the transmission gate is turned on, it transfers the input pattern bits to the output line.

Abstract: An integrated circuit for digitizing a dynamic waveform with a resolution that is much higher than that which is achievable under prior art methods is disclosed. A reference clock signal T.sub.r is provided as input to at least two L-type registers over a synchronous delay line (SDL). The reference clock signal is also coupled to the L ports of the L-type registers over a sample enable circuit. The incoming waveform is input in parallel to both L-type registers. The SDL generates timing pulses at intervals that are separated by T.sub.r /N, where N is the number of taps in the SDL. N corresponds to the equally spaced intervals at which the incoming waveform is sampled. The L-type register samples the incoming waveform according to control signals provided by the sample enable circuit. The control signals are required to guarantee the set-up and hold times for the flip-flops in the L-type register. Thus, the resolution of the digitized waveform is T.sub.r /N.