Abstract: An automatic reset scheme for a synchronized delay line detects the polarity of the tap signals from a predetermined number of delay stages. If the delay line powers up to lock onto one of the non-fundamental modes of operation, an inverted polarity is detected at the output of one of the selected taps coupled to the reset circuit and an automatic reset is initiated for the delay line.

Abstract: A CMOS complementary, self-biased, differential amplifier provides for a rail-to-rail common-mode input-voltage range of operation. A self-biasing scheme is used to provide negative feedback to the amplifier in order to assist in providing a common-mode rejection but providing high gain amplification for differential-mode amplification.

Abstract: A self-biased, high-gain differential amplifier which is substantially immune to process and temperature variations. A first pair of CMOS transistors is coupled to operate in an active region and an output from the common junction is coupled to drive a second pair of CMOS transistors. The second pair of CMOS transistors have their outputs coupled to provide a negative feedback to the first pair of CMOS transistors. A third pair of CMOS transistors is coupled in parallel to the first pair of CMOS transistors for accepting an input signal and generating an output, wherein the output is a function of the input signal in relation to a reference voltage. A fourth pair of CMOS transistors is coupled to be driven by the third pair of CMOS transistors and provides a CMOS compatible signal which switches between two CMOS logic states.

Abstract: An input buffer circuit for providing corresponding CMOS compatible signals to an input signal. The input buffer circuit is comprised of a switched-capacitor voltage division network for providing a reference voltage to a comparator. The comparator accepts an input voltage and determines if the input voltage is greater or less than the reference voltage and generates a CMOS compatible output, which is determined by the value of the input signal in reference to the reference voltage. The reference voltage generator is comprised of two capacitive devices, wherein the first capacitive device is charged and the second capacitive device is discharged during a first time period and the charges on the two capacitive devices are shared during a second time period. A ratio of the capacitances of these two capacitive devices determines the voltage value at the junction of the two capacitors, which then determines the reference voltage.

Abstract: A finite state machine suitable for MOS fabrication is described. The finite state machine includes a programmed logic array (PLA). The PLA AND plane includes logical inputs and state signal inputs. The state signal inputs are decoded binomially. The state signals are used to activate the AND plane loads, thereby avoiding the necessity of using either a constantly active pull-up or precharge/selective discharge circuitry technique.

Abstract: An operational amplifier suitable for MOS fabrication is described. The amplifier operates adequately over a large range of process, temperature and voltage supply variations. Two identical delay lines are employed in the amplifier. One controls the frequency of oscillation of an oscillator. The oscillator's output is used to control a sample-and-hold circuit, is delayed through the second delay circuit, and is used through a gate circuit to provide a sampled potential for the sample-and-hold circuit.

Abstract: A synchronized delay line is described which is tapped to provide a plurality of timing signals. The delay line is insensitive to voltage changes, temperature changes and wafer processing variations. It is ideally suited for providing on-chip timing signals derived from a reference clock for MOS integrated circuits.