Abstract: The present application discloses a method of fabricating a thin film transistor, including forming a semiconductor layer having a pattern corresponding to that of the active layer on a base substrate; forming a first photoresist layer on a side of the semiconductor layer distal to the base substrate; the first photoresist layer being in an area corresponding to the channel region, the second doped region, and the fourth doped region; doping a region of the semiconductor layer corresponding to the first doped region and the third doped region using the first photoresist layer as a mask plate; forming a second photoresist layer by removing a portion of the first photoresist layer to expose an initial portion of the semiconductor layer corresponding to at least a portion of the second doped region and at least a portion of the fourth doped region; and doping the initial portion of the semiconductor layer using the second photoresist layer as a mask plate.

Abstract: The present invention discloses a safety protection method of dynamic detection for mobile robots. The mobile robot is provided with a sensor. Said sensor obtains the obstacle information in the detection areas in front of a mobile robot, and the mobile robot is caused to progressively slow down and dynamically adjust the detection area when an obstacle appears in the detection area. If no obstacle is detected in the detection area after adjusting, then the mobile robot is caused to keep on moving, and if an obstacle is still detected in the detection area after adjusting, then the mobile robot is caused to keep on decelerating until they are stopped. The sensor sets different detection areas according to the traveling speed and traveling direction of the mobile robot, or presets the detection area according to the path and dynamically adjusts it when the mobile robot is running.

Abstract: A method, and an apparatus for recommending an interface theme are provided. An exemplary embodiment of the method includes: obtaining a target image which includes an image of a target person; obtaining characteristic information of the target person based on the target image; obtaining a selection list of recommended themes, wherein the recommended themes are interface themes that match the characteristic information of the target person; and outputting the selection list of recommended themes.

Abstract: As disclosed herein a method, executed by a computer, for automatically determining a workflow completion state includes initiating a workflow including one or more jobs, receiving a notification that a first job corresponding to the workflow has finished, checking dependency requirements of a successor job corresponding to the first job, submitting the successor job for processing if the dependency requirements have been satisfied, and evaluating a completion status of each of the one or more jobs to determine whether the workflow is still running. Complex workflows may consist of many jobs, all of which may not be required to complete for the workflow to complete successfully. The method described herein enables the completion state of a workflow to be determined without requiring user defined completion criteria. A computer system, and computer program product corresponding to the method are also disclosed herein.

Abstract: As disclosed herein a method, executed by a computer, for automatically determining a workflow completion state includes initiating a workflow including one or more jobs, receiving a notification that a first job corresponding to the workflow has finished, checking dependency requirements of a successor job corresponding to the first job, submitting the successor job for processing if the dependency requirements have been satisfied, and evaluating a completion status of each of the one or more jobs to determine whether the workflow is still running. Complex workflows may consist of many jobs, all of which may not be required to complete for the workflow to complete successfully. The method described herein enables the completion state of a workflow to be determined without requiring user defined completion criteria.

Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Abstract: Work flows consist of the following steps: (i) receiving a work flow data set that defines a work flow which includes a plurality of work items; and (ii) defining, a centralized and pattern-based work flow level job input/output (I/O) characteristic set that includes at least I/O settings for work items included in the work flow.

Abstract: An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.

Abstract: A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.

Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.

Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract: An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

Abstract: A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.