Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are selected and the appropriate programming voltages are established at their wordlines and bitlines. Unselected wordlines in the array are biased with a slight negative bias voltage to reduce or eliminate leakage bitline current that might otherwise conduct through the memory cells. A slight negative wordline bias voltage may also be applied to unselected cells during verification operations (program verify, soft program verify, erase verify) and read operations to reduce or eliminate leakage current that might otherwise introduce errors in the verification and read operations.

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract: A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory device may be efficiently erased using Fowler-Nordheim tunneling.

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.

Abstract: According to one exemplary embodiment, a structure, for example a flash memory cell, comprises a transistor gate dielectric stack situated on a semiconductor substrate. The transistor gate dielectric stack includes a bottom oxide layer, a silicon-rich nitride layer situated on the bottom oxide layer, a low silicon-rich nitride layer situated on the silicon-rich nitride layer, and a top oxide layer situated on the low silicon-rich nitride layer. This embodiment results in a nitride based flash memory cell having improved program speed and retention while maintaining a high erase speed. In another embodiment, a flash memory cell may further comprise a high-K dielectric layer situated on the transistor gate dielectric stack.

Abstract: A method for making a magnetoresistive read head so that the pinned ferromagnetic layer is wider than the stripe height of the free ferromagnetic layer uses ion milling with the ion beam aligned at an angle to the substrate supporting the stack of layers making up the read head. The stack is patterned with photoresist to define a rectangular region with front and back long edges aligned parallel to the read head track width. After ion milling in two opposite directions orthogonal to the front and back long edges, the pinned layer width has an extension. The extension makes the width of the pinned layer greater than the stripe height of the free layer after the substrate and stack of layers are lapped. The length of the extension is determined by the angle between the substrate and the ion beam and the thickness of the photoresist.

Abstract: A device according to one embodiment includes an electronic component such as an MR sensor, a pair of leads operatively coupled to the electronic component, and shorting material between the leads, the shorting material having been applied by a laser deposition process, the shorting material having been severed. A magnetic storage system according to another embodiment includes magnetic media; and at least one head for reading from and writing to the magnetic media, each head having: a sensor; and a writer coupled to the sensor. The system also includes a pair of pads or leads operatively coupled to the head; shorting material between the leads, the shorting material having been applied by a laser deposition process, the shorting material having been severed; a slider for supporting the head; and a control unit coupled to the head for controlling operation of the head.

Abstract: According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between two adjacent trenches, and where each of the wordline regions have a wordline region width. The memory array can be a flash memory array. The method further includes forming a number of bitlines in the substrate, where the bitlines are situated perpendicular to the trenches. The method further includes forming a dielectric region in each of the trenches. The method further includes forming a dielectric stack over the bitlines, wordline regions, and trenches. The method further includes forming a number of wordlines, where each wordline is situated over one of the wordline regions. The wordline region width determines an active wordline width of each of the wordlines.

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a first intermediate layer over the first insulator layer, forming a charge trap layer over the first intermediate layer, forming a second intermediate layer over the charge trap layer, and forming a second insulator layer with the second intermediate layer.

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer having a gradient of a silicon above and below the charge trap layer over the first insulator layer, and forming a second insulator layer over the charge trap layer.

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.

Abstract: A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.

Abstract: A method of making a read sensor while protecting it from electrostatic discharge (ESD) damage involves forming a severable shunt during the formation of the read sensor. The method may include forming a resist layer over a plurality of read sensor layers; performing lithography with use of a mask to form the resist layer into a patterned resist which exposes left and right side regions over the read sensor layers as well as a shunt region; etching, with the patterned resist in place, to remove materials in the left and right side regions and in the shunt region; and depositing, with the patterned resist in place, left and right hard bias and lead layers in the left and right side regions, respectively, and in the shunt region for forming a severable shunt which electrically couples the left and right hard bias and lead layers together for ESD protection.

Abstract: A memory includes a first charge storage region spaced apart from a second charge storage region by an isolation region. Techniques for erasing a memory are provided in which electrons are Fowler-Nordheim (FN) tunneled out of at least one of the charge storage regions into a substrate to erase the at least one charge storage region of the memory. Other techniques are provided for programming a single charge storage region at multiple different levels or states.

Abstract: A dual-bit memory device includes a first charge storage region spaced apart from a second charge storage region by an isolation region. Techniques for erasing a memory can be provided in which electrons can be injected into the charge storage regions to erase the charge storage regions. Other techniques for programming a memory can be provided in which holes can be injected into at least one of the charge storage regions to program the charge storage regions.

Abstract: A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN or PNP diode reduces device damage and performance impairment that may result from device charging by drawing charges away from the memory device.

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Abstract: A device according to one embodiment includes an electronic component such as an MR sensor, a pair of leads operatively coupled to the electronic component, and shorting material between the leads, the shorting material having been applied by a laser deposition process, the shorting material having been severed. A magnetic storage system according to another embodiment includes magnetic media; and at least one head for reading from and writing to the magnetic media, each head having: a sensor; and a writer coupled to the sensor. The system also includes a pair of pads or leads operatively coupled to the head; shorting material between the leads, the shorting material having been applied by a laser deposition process, the shorting material having been severed; a slider for supporting the head; and a control unit coupled to the head for controlling operation of the head.

Abstract: A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.

Abstract: A method for shorting, unshorting, and reshorting an electronic component such as an MR sensor provides a repeatable ESD protection scheme. A conductive line of an electrically conductive first shorting material is created between electrical leads operatively coupled to an electronic component for creating a short therebetween. The short is severed using a laser. The short is recreated by applying a second shorting material, which may or may not be the same as the first shorting material.