Abstract: An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

Abstract: A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

Abstract: A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and electrically connected to the p-type substrate via a first metal line, a well of p-type material formed in the first well of n-type material, a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and connected to the word line of the memory device, and a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and electrically connected to the well of p-type material via a second metal line.

Abstract: A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

Abstract: According to one exemplary embodiment, a two-bit memory cell includes a gate stack situated over a substrate, where the gate stack includes a charge-trapping layer. The charge-trapping layer includes first and second conductive segments and a nitride segment, where the nitride segment is situated between the first and second conductive segments. The nitride segment electrically insulates the first conductive segment from the second conductive segment. The first and second conductive segments provide respective first and second data bit storage locations in the two-bit memory cell. The gate stack can further include a lower oxide segment situated between the substrate and the charge-trapping layer. The gate stack can further include an upper oxide segment situated over the charge-trapping layer. The gate stack can be situated between a first dielectric segment and a second dielectric segment, where the first and second dielectric segments are situated over respective first and second bitlines.

Abstract: One illustrative method of fabricating a read sensor of a magnetic head includes the steps of forming a plurality of read sensor layers on a wafer; etching the read sensor layers to form a read sensor structure with a trench in front of the read sensor structure; forming a highly porous material within the trench; and slicing the wafer and lapping the sliced wafer through the highly porous material until an air bearing surface (ABS) of the magnetic head is reached. Advantageously, the highly porous material in front of the read sensor structure reduces mechanical stress on the read sensor during the lapping process. This reduces the likelihood that the amplitude of the read sensor will be degraded or set in a “flipped” or reversed orientation, as well as reduces the likelihood that electrostatic discharge (ESD) damage to the read sensor will occur.

Abstract: A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

Abstract: A self pinned magnetoresistive sensor that has a relatively thick compressive material at either side to assist with self pinning. A shield having recessed portions at either side of the sensor area allows room for a thicker compressive layer than would otherwise be possible.

Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are selected and the appropriate programming voltages are established at their wordlines and bitlines. Unselected wordlines in the array are biased with a slight negative bias voltage to reduce or eliminate leakage bitline current that might otherwise conduct through the memory cells. A slight negative wordline bias voltage may also be applied to unselected cells during verification operations (program verify, soft program verify, erase verify) and read operations to reduce or eliminate leakage current that might otherwise introduce errors in the verification and read operations.

Abstract: An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

Abstract: A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.

Abstract: A dual-bit memory device includes a first charge storage region spaced apart from a second charge storage region by an isolation region. Techniques for erasing a memory can be provided in which electrons can be injected into the charge storage regions to erase the charge storage regions. Other techniques for programming a memory can be provided in which holes can be injected into at least one of the charge storage regions to program the charge storage regions.

Abstract: A memory system includes a substrate, forming a first insulator over the substrate, forming a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator, and forming a second insulator over the charge trap layer.

Abstract: A memory system includes a substrate, forming a first insulator layer over the substrate, forming a charge-storage layer over the first insulator layer, forming a second insulator layer over the charge-storage layer, and forming a depletion gate having a depletion phenomenon over the second insulator layer.

Abstract: A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.