Abstract: Disclosed are a sound generator and an audio device. The sound generator includes a magnetically conductive plate, a first magnetic structure, a second magnetic structure, a treble diaphragm, a treble voice coil, a bass diaphragm and a bass voice coil. The first magnetic structure includes a first washer including a first sub-washer located and a second sub-washer provided surrounding the first sub-washer, and a treble magnetic gap is formed between the first sub-washer and the second sub-washer. A bass magnetic gap is formed between the first magnetic structure and the second magnetic structure. The treble voice coil is provided on a side of the treble diaphragm close to the magnetically conductive plate and is provided corresponding to the treble magnetic gap. The bass voice coil is provided on a side of the bass diaphragm close to the magnetically conductive plate and is provided corresponding to the bass magnetic gap.

Abstract: A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.

Abstract: The invention discloses a serial high-temperature gas-cooled reactor nuclear energy system and an operating method thereof. The serial high-temperature gas-cooled reactor nuclear energy system includes a plurality of high-temperature gas-cooled reactors and a serial gas-cooled reactor. The high-temperature gas-cooled reactor includes a first reactor pressure vessel comprising a first reaction chamber for accommodating the first fuel element; a second reactor pressure vessel comprising a second reaction chamber interconnected with the first reaction chamber, allowing the first spent fuel in the first reaction chamber to enter the second reaction chamber.

Abstract: An air-ground joint trajectory planning and offloading scheduling method and system for distributed multiple objectives is provided. At the beginning of each timeslot, an unmanned aerial vehicle (UAV) selects a flight direction based on a total energy consumption of all devices and a total amount of unprocessed data of all the devices in the current system, and flies a fixed distance towards a certain direction. Before the UAV reaches a new location, each terrestrial user independently selects a task data offloading scheduling strategy based on the total energy consumption of all the devices and the total amount of the unprocessed data of all the devices in the current system. In order to improve an expected long-term average energy efficiency and data processing capability, the present disclosure also provides average feedbacks for an energy consumption and unprocessed data.

Abstract: Provided are a bovine rotavirus fusion protein and calf diarrhea multivalent vaccine. The bovine rotavirus fusion protein contains a VP6 fragment, wherein the VP6 fragment contains an amino acid sequence as represented by SEQ ID NO. 4, and at least one loop region of the following (a)˜(c) is substituted with an antigenic epitope derived from bovine coronavirus and/or an antigenic epitope derived from E. coli: (a) amino acid residues of sites 168-177; with an amino acid sequence as represented by SEQ ID NO. 1; (b) amino acid residues of sites 194-205; with an amino acid sequence as represented by SEQ ID NO. 2; and (a) amino acid residues of sites 296-316, with an amino acid sequence as represented by SEQ ID NO. 3, The bovine rotavirus fusion protein contains a plurality of antigenic epitopes, and can enable a host to generate a plurality of antibodies after immunizing the host.

Abstract: An integrated circuit apparatus includes a substrate and a well contact that is disposed on the substrate. The well contact includes first and second source/drain structures that are disposed on the substrate; a metal vertical portion that contacts the substrate immediately between the first and second source/drain structures; inner spacers that electrically insulate the vertical portion from the adjacent source/drain structures; bottom dielectric isolation that electrically insulates the source/drain structures from the substrate; and a well portion that is embedded into the substrate in registry with the vertical portion. The well portion is doped differently than the substrate.

Abstract: An integrated circuit is presented including a protection diode including a plurality of first gates and a plurality of first source/drain (S/D) contacts and a device under test (DUT) including a plurality of second gates and a plurality of second S/D contacts, the DUT being electrically connected to the protection diode by either at least one gate contact or at least on CA contact or at least one buried power rail (BPR). The protection diode is electrically connected to the DUT by middle-of-line (MOL) layers for gate oxide protection before M1 formation.

Abstract: Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.

Abstract: A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, and a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the second source/drain region comprises a recessed notch beneath the first source/drain region.

Abstract: A semiconductor device structure and methodology for determining a power consumption of the device structure and to extract accurate real temperatures due to self-heating effects. The semiconductor device structure includes a first transistor device formed as a heater device and an adjacent device such as a second transistor device or a semiconductor junction device. In the method, the first transistor device is operable at different operating states (e.g., off state or at different applied power levels), and at each state, an electrical characteristic is measured at the adjacent second transistor device or junction device. The electrical characteristic measured at the adjacent second semiconductor device is correlated to a power consumption of the first device while excluding a power consumption due to voltage drops due to resistance of connected metal layers, vias or contacts.

Abstract: Metal-insulator-metal capacitor designs with increased reliability are provided. In one aspect, a capacitor includes: first and second electrodes; and multiple dielectric layers present in between the first and second electrodes, including a first buffer layer disposed on the first electrode, a ferroelectric film disposed on the first buffer layer, and a second buffer layer disposed on the ferroelectric film, where the ferroelectric film includes a combination of at least a first dielectric material and a second dielectric material having a higher ? value than either the first or second buffer layers. The first and second dielectric materials can each include HfO2 and/or ZrO2, in a crystalline phase, which can be combined in a common layer, or present in different layers. A capacitor device having the present capacitors stacked one on top of another is also provided, as is a method of forming the present capacitors.

Abstract: A semiconductor structure including a gate-all-around input/output (I/O) device and a gate-all-around core logic device integrated on a semiconductor substrate is provided. The gate-all-around I/O device, which has a wider channel length than the gate-all-around core logic device, has a dielectric spacer and/or inner spacers that is (are) laterally wider (i.e., thicker) than a dielectric spacer and/or inner spacers present in the gate-all-around core logic device.

Abstract: A ring oscillator circuit design includes three or more inverter stages connected in series. Each inverter stage includes one or more inverter devices including a PMOS device and a coupled NMOS device. The PMOS device in each of odd alternating inverter devices of the three or more inverter stages having a source terminal receiving power from a power rail conductor, and a source terminal of the coupled NMOS device in each of first alternating inverter devices is grounded. An output of a last inverter device of a last stage of the three or more inverter stages is connected to an input of a first inverter stage. The method measures a first frequency of a first ring oscillator circuit and measures a second frequency of a second ring oscillator circuit design to determine either a BTI or HCI failure mechanism of the first ring oscillator circuit based on the measurements.

Abstract: Embodiments of present invention provide a static random-access-memory (SRAM) device. The SRAM device includes a first set of nanosheets used in an n-type transistor; and a second set of nanosheets with one or more nanosheets of the second set of nanosheets used in a p-type transistor, wherein a width of the second set of nanosheets is wider than a width of the first set of nanosheets. In one embodiment the p-type transistor is used as a pull-up transistor and the n-type transistor is used as a pull-down transistor or a pass-gate transistor. A method of manufacturing the SRAM device is also provided.

Abstract: Fabrication method for forming a resistance tunable fuse stack structure includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer, a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting at least one of the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse contacts.

Abstract: Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.

Abstract: Vertically stacked, buried power rails are electrically connected to wrap-around contacts or other electrically conductive liners on transistor source/drain regions. The buried power rails are electrically isolated from each other by an electrical insulator. Wrap-around contacts can be electrically connected to different ones of the vertically stacked, buried power rails or to the same buried power rail.

Abstract: A semiconductor structure comprises a first nanosheet device having at least one first channel layer and a first gate, a second nanosheet device disposed above the first nanosheet device and having at least one second channel layer and a second gate, and an isolation layer disposed between the first nanosheet device and the second nanosheet device to electrically isolate the first nanosheet device and the second nanosheet device.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment of the invention, a GAA nanosheet device is formed in a first region of a substrate. The GAA nanosheet device includes a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack. A comb-nanosheet device is formed in a second region of a substrate. The comb-nanosheet device includes a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack that is less than the first fin spacing distance.

Abstract: Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.