Abstract: A semiconductor device comprises a stacked structure comprising a plurality of gate structures alternately stacked with a plurality of channel structures. Respective ones of the plurality of channel structures comprise a plurality of stacked semiconductor layers. At least two of the plurality of stacked semiconductor layers in the respective ones of the plurality of channel structures comprise different materials from each other.

Abstract: A semiconductor device comprises a stacked structure comprising a plurality of gate structures alternately stacked with a plurality of dielectric layers. Respective ones of the plurality of gate structures comprise a gate region and a gate dielectric layer disposed around the gate region. Respective ones of the plurality of dielectric layers are disposed between a first two-dimensional semiconductor material layer of a plurality of two-dimensional semiconductor material layers and a second two-dimensional semiconductor material layer of the plurality of two-dimensional semiconductor material layers. The gate dielectric layer of the respective ones of the plurality of gate structures contacts at least one of the plurality of two-dimensional semiconductor material layers.

Abstract: An in-situ chip design is provided for self-heating free characterization of a device under test (DUT) with a short time constant. The in-situ chip design includes a pulse generator configured to output a pulse to the DUT and a buffering circuit arranged between the pulse generator and the DUT. The buffering circuit includes a first switch and an adjustable buffer circuit in parallel with the first switch and being controllable to apply one of various degrees of buffering to the pulse.

Abstract: A semiconductor device includes a metal-insulator-metal capacitor disposed between a first metallization level and a second metallization level, the metal-insulator-metal capacitor comprising a first electrode, a second electrode and a third electrode. A first via is extended from and contacts a conductive line of the second metallization level, and a second via is extended from and contacts the first via. The second via contacts the first electrode and the third electrode of the metal-insulator-metal capacitor. A slope of a side surface of the first via is different from a slope of a side surface of the second via.

Abstract: Embodiments of present invention provide a test structure. The test structure includes a scribe line area in a semiconductor substrate; a first fin and a second fin in the scribe line area and an insulating region between the first fin and the second fin; a first epitaxial region directly on top of the first fin and a second epitaxial region directly on top of the second fin; and an under-test region on top of the insulating region in the scribe line area and between the first epitaxial region and the second epitaxial region. In one aspect, the under-test region includes a gate and a first and a second sidewall spacer formed at a first and a second sidewall of the gate, the first epitaxial region being in contact with the first sidewall spacer and the second epitaxial region being in contact with the second sidewall spacer.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a first stacked field effect transistor (FET) structure in a first device area, the first stacked FET structure comprising a first pull down (PD) transistor, and a first pull up (PU) transistor disposed over the first PD transistor, a first metal gate that is shared by the first PD transistor and the first PU transistor; and an oxygen blocking layer provided on the first metal gate.

Abstract: A semiconductor test structure includes a first transistor active area comprising at least a first source/drain region, and a second transistor active area stacked on the first transistor active area and comprising at least a second source/drain region. At least one dielectric layer is disposed between the first transistor active area and the second transistor active area. The semiconductor test structure further includes a plurality of contact structures spaced apart from each other and disposed on the second source/drain region, and at least one gate structure extending across the first transistor active area and the second transistor active area. Contact resistance is measured between respective ones of the plurality of contact structures and the second source/drain region, and the second source/drain region is continuous between the plurality of contact structures.

Abstract: The disclosure provides a fine-grain tin-phosphor bronze alloy strip and a preparation method thereof. The fine-grain tin-phosphor bronze alloy strip comprises the following elements in percentage by mass: 4.0-10 wt % of Sn, 0.01-0.3 wt % of P and the balance of Cu and inevitable impurity elements, the average grain size of the tin-phosphor bronze alloy strip is 1-3 ?m, the grain size is in normal distribution, and the standard deviation of the grain size is 0.9 ?m or below; the proportion of the total low-?CSL grain boundary in the tin-phosphor bronze alloy strip in the whole grain boundary is 66-74%, and in the total low-?CSL grain boundary, the ratio range of (?9+?27)/?3 is 0.12-0.23:1. The fine-grain tin-phosphor bronze alloy strip of this disclosure enables a finished strip can have the tensile strength and the excellent bending performance at the same time.

Abstract: The disclosure provides a modified tin-phosphor bronze alloy and a preparation method thereof. The modified tin-phosphor bronze alloy comprises the following elements in percentage by mass: 4.0-10 wt % of Sn, 0.01-0.3 wt % of P and the balance of Cu and inevitable impurity elements, the average grain size of the modified tin-phosphor bronze alloy is 1-3 ?m, the grain size is in normal distribution, and the standard deviation of the grain size is below 0.8 ?m; the proportion of the total low-CSL grain boundary in the modified tin-phosphor bronze alloy in the whole grain boundary is 66-74%, and in the total low-?CSL grain boundary, the ratio range of (?9+?27)/?3 is (0.12-0.23):1. The modified tin-phosphor bronze alloy of this disclosure enables a finished alloy can give consideration to both tensile strength and excellent bending performance.

Abstract: In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.

Abstract: Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.

Abstract: Disclosed is an intelligent head-mounted apparatus, comprising: a lens; a leg coupled to the lens and provided with a cavity therein; a sound generation device provided in the cavity and dividing the cavity into front and rear sound cavities; a sound outlet hole provided on the leg and in communication with the front sound cavity; main and auxiliary sound leakage holes provided on the leg and in communication with the rear sound cavity, positions of the sound outlet hole, the main sound leakage hole and the auxiliary sound leakage hole are configured such that the sound outlet hole and the auxiliary sound leakage hole are located at a front side of an auricle of a wearer, the main sound leakage hole is located at a rear side of the auricle of the wearer when the wearer wears the intelligent head-mounted apparatus.

Abstract: Fabrication method for forming a resistance tunable fuse stack structure includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer, a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting at least one of the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse contacts.

Abstract: A device and a method for determining a microvibration effect on a millisecond-level space optical sensor are provided. The device includes: a light source, a star simulator, an air flotation vibration isolation platform, a suspension system/air flotation system, a zero stiffness system, a supporting system, a six-degree-of-freedom microvibration simulator, a signal driving apparatus, and a data acquisition and processing system. In the device for determining a microvibration effect on a space pointing measurement apparatus, a free boundary condition and a zero gravity environment are simulated by using a suspension system and a zero stiffness system. A light source and a star simulator simulate a star at infinity. A six-degree-of-freedom microvibration simulator simulates an on-orbit microvibration mechanical environment which is used as an input of a test. Extremely high-precision sensors collect system response data.

Abstract: Provided herein are methods and compositions useful for treating bacterial cell populations including bacterial persister cells and/or antibiotic resistant bacterial cells.

Abstract: Embodiments of present invention provide a method of forming a gate structure of a transistor. The method includes forming a channel region of the gate structure; forming a high-k dielectric layer covering the channel region; forming a silicon monolayer covering the high-k dielectric layer; forming a sacrificial metal layer covering the silicon monolayer; forming a sacrificial silicon layer covering the sacrificial metal layer; subjecting the gate structure to a thermal anneal process, thereby transforming the silicon monolayer into a nitrogen-containing monolayer; removing the sacrificial silicon layer and the sacrificial metal layer; and forming a gate metal surrounding the channel region of the gate structure. A gate structure formed thereby is also provided.

Abstract: Disclosed are a sound generator and an audio device. The sound generator includes a magnetically conductive plate, a first magnetic structure, a second magnetic structure, a treble diaphragm, a treble voice coil, a bass diaphragm and a bass voice coil. The first magnetic structure includes a first washer including a first sub-washer located and a second sub-washer provided surrounding the first sub-washer, and a treble magnetic gap is formed between the first sub-washer and the second sub-washer. A bass magnetic gap is formed between the first magnetic structure and the second magnetic structure. The treble voice coil is provided on a side of the treble diaphragm close to the magnetically conductive plate and is provided corresponding to the treble magnetic gap. The bass voice coil is provided on a side of the bass diaphragm close to the magnetically conductive plate and is provided corresponding to the bass magnetic gap.

Abstract: A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.

Abstract: The invention discloses a serial high-temperature gas-cooled reactor nuclear energy system and an operating method thereof. The serial high-temperature gas-cooled reactor nuclear energy system includes a plurality of high-temperature gas-cooled reactors and a serial gas-cooled reactor. The high-temperature gas-cooled reactor includes a first reactor pressure vessel comprising a first reaction chamber for accommodating the first fuel element; a second reactor pressure vessel comprising a second reaction chamber interconnected with the first reaction chamber, allowing the first spent fuel in the first reaction chamber to enter the second reaction chamber.

Abstract: An integrated circuit apparatus includes a substrate and a well contact that is disposed on the substrate. The well contact includes first and second source/drain structures that are disposed on the substrate; a metal vertical portion that contacts the substrate immediately between the first and second source/drain structures; inner spacers that electrically insulate the vertical portion from the adjacent source/drain structures; bottom dielectric isolation that electrically insulates the source/drain structures from the substrate; and a well portion that is embedded into the substrate in registry with the vertical portion. The well portion is doped differently than the substrate.