Abstract: Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.

Abstract: A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, and a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the second source/drain region comprises a recessed notch beneath the first source/drain region.

Abstract: A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.

Abstract: Disclosed is an intelligent head-mounted apparatus, comprising: a lens; a leg coupled to the lens and provided with a cavity therein; a sound generation device provided in the cavity and dividing the cavity into a front sound cavity and a rear sound cavity; a sound outlet hole provided on the leg and in communication with the front sound cavity; and a main sound leakage hole provided on the leg and in communication with the rear sound cavity, wherein positions of the sound outlet hole and the main sound leakage hole are configured such that the sound outlet hole is located at a front side of an auricle of a wearer, and the main sound leakage hole is located at a rear side of the auricle of the wearer when the wearer wears the intelligent head-mounted apparatus.

Abstract: Disclosed is an intelligent head-mounted apparatus, comprising: a lens; a leg coupled to the lens and provided with a cavity therein; a sound generation device provided in the cavity and dividing the cavity into front and rear sound cavities; a sound outlet hole provided on the leg and in communication with the front sound cavity; main and auxiliary sound leakage holes provided on the leg and in communication with the rear sound cavity, positions of the sound outlet hole, the main sound leakage hole and the auxiliary sound leakage hole are configured such that the sound outlet hole and the auxiliary sound leakage hole are located at a front side of an auricle of a wearer, the main sound leakage hole is located at a rear side of the auricle of the wearer when the wearer wears the intelligent head-mounted apparatus.

Abstract: In a rotary motion detecting device that outputs a signal corresponding to rotary motion of a rotary disk coupled to a shaft, a boss is fixed to the shaft, the boss is fixed to one surface of the rotary disk, and one of the boss and the shaft is a hole member having a hole formed therein and the other is an inserted member that is inserted in the hole. The hole member has an inner periphery (inner diameter) that is larger than an outer periphery (outer diameter) of the inserted member so that the shaft can be vertical to the rotary disk without being restricted by the boss.

Abstract: An analysis device obtains connection states of a testing terminal pair that respectively correspond to a plurality of unit moments in a first historical time segment. The testing terminal pair includes a first terminal and a second terminal, the first historical time segment is a time segment before a current time, the first historical time segment includes M consecutive unit moments, and M is a natural number greater than or equal to 2. The analysis device determines, based on the connection states of the testing terminal pair that respectively correspond to the plurality of unit moments in the first historical time segment, a connection state that is of the testing terminal pair and that corresponds to at least one unit moment in a future time segment.

Abstract: Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.

Abstract: A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers.

Abstract: A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter- layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse electrical contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers.

Abstract: A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse electrical contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers.

Abstract: In a rotary motion detecting device that outputs a signal corresponding to rotary motion of a rotary disk coupled to a shaft, a boss is fixed to the shaft, the boss is fixed to one surface of the rotary disk, and one of the boss and the shaft is a hole member having a hole formed therein and the other is an inserted member that is inserted in the hole. The hole member has an inner periphery (inner diameter) that is larger than an outer periphery (outer diameter) of the inserted member so that the shaft can be vertical to the rotary disk without being restricted by the boss.

Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin. A first source/drain contacts the semiconductor fin. An interfacial layer contacts sidewalls of the semiconductor fin. An insulating layer contacts the interfacial layer. One or more conductive gate layers encapsulate the interfacial and insulating layers. A second source/drain is formed above the first source/drain. The method comprises forming at least one semiconductor fin. An interfacial layer is formed in contact with sidewalls of the semiconductor fin. An insulating layer is formed in contact with the interfacial layer. The interfacial layer and the insulating layer are encapsulated by one or more conductive gate layers.

Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.

Abstract: A semiconductor device comprising an anti-fuse is disclosed. The semiconductor anti-fuse includes a highly doped source of a first conductivity type overlying a substrate. The semiconductor anti-fuse further includes a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate. The semiconductor anti-fuse further includes a highly doped fuse region extending over the highly doped source and comprising an epitaxial growth, the highly doped fuse region implanted with ions.

Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.

Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin. A first source/drain contacts the semiconductor fin. An interfacial layer contacts sidewalls of the semiconductor fin. An insulating layer contacts the interfacial layer. One or more conductive gate layers encapsulate the interfacial and insulating layers. A second source/drain is formed above the first source/drain. The method comprises forming at least one semiconductor fin. An interfacial layer is formed in contact with sidewalls of the semiconductor fin. An insulating layer is formed in contact with the interfacial layer. The interfacial layer and the insulating layer are encapsulated by one or more conductive gate layers.

Abstract: A back-end-of-the-line (BEOL) anti-fuse of a BEOL structure is disclosed. The anti-fuse structure includes a metallization layer formed in a first insulator layer of the BEOL structure. The metallization layer has a trench formed therein. The trench has substantially vertical sidewalls and angled sidewalls formed underlying the vertical sidewalls, the angled sidewalls angled to meet at an apex. The anti-fuse structure further includes a second insulator formed on the vertical sidewalls and the angled sidewalls. The anti-fuse structure further includes a metallic via formed on the second insulator in the trench.