Patents by Inventor Miaomiao Wang

Miaomiao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096871
    Abstract: An integrated circuit is presented including a protection diode including a plurality of first gates and a plurality of first source/drain (S/D) contacts and a device under test (DUT) including a plurality of second gates and a plurality of second S/D contacts, the DUT being electrically connected to the protection diode by either at least one gate contact or at least on CA contact or at least one buried power rail (BPR). The protection diode is electrically connected to the DUT by middle-of-line (MOL) layers for gate oxide protection before M1 formation.
    Type: Application
    Filed: September 19, 2022
    Publication date: March 21, 2024
    Inventors: Huimei Zhou, Terence Hook, Junli Wang, Miaomiao Wang
  • Patent number: 11908743
    Abstract: Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: February 20, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huimei Zhou, Andrew M. Greene, Julien Frougier, Ruqiang Bao, Jingyun Zhang, Miaomiao Wang, Dechao Guo
  • Patent number: 11869812
    Abstract: A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, and a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the second source/drain region comprises a recessed notch beneath the first source/drain region.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Huimei Zhou, Miaomiao Wang, Alexander Reznicek
  • Publication number: 20230417604
    Abstract: A semiconductor device structure and methodology for determining a power consumption of the device structure and to extract accurate real temperatures due to self-heating effects. The semiconductor device structure includes a first transistor device formed as a heater device and an adjacent device such as a second transistor device or a semiconductor junction device. In the method, the first transistor device is operable at different operating states (e.g., off state or at different applied power levels), and at each state, an electrical characteristic is measured at the adjacent second transistor device or junction device. The electrical characteristic measured at the adjacent second semiconductor device is correlated to a power consumption of the first device while excluding a power consumption due to voltage drops due to resistance of connected metal layers, vias or contacts.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Inventors: HUIMEI ZHOU, MIAOMIAO WANG, Effendi Leobandung
  • Publication number: 20230420491
    Abstract: Metal-insulator-metal capacitor designs with increased reliability are provided. In one aspect, a capacitor includes: first and second electrodes; and multiple dielectric layers present in between the first and second electrodes, including a first buffer layer disposed on the first electrode, a ferroelectric film disposed on the first buffer layer, and a second buffer layer disposed on the ferroelectric film, where the ferroelectric film includes a combination of at least a first dielectric material and a second dielectric material having a higher ? value than either the first or second buffer layers. The first and second dielectric materials can each include HfO2 and/or ZrO2, in a crystalline phase, which can be combined in a common layer, or present in different layers. A capacitor device having the present capacitors stacked one on top of another is also provided, as is a method of forming the present capacitors.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: Kisik Choi, Paul Charles Jamison, Takashi Ando, Lawrence A. Clevenger, Huimei Zhou, Miaomiao Wang, Ernest Y. Wu
  • Publication number: 20230411392
    Abstract: A semiconductor structure including a gate-all-around input/output (I/O) device and a gate-all-around core logic device integrated on a semiconductor substrate is provided. The gate-all-around I/O device, which has a wider channel length than the gate-all-around core logic device, has a dielectric spacer and/or inner spacers that is (are) laterally wider (i.e., thicker) than a dielectric spacer and/or inner spacers present in the gate-all-around core logic device.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 21, 2023
    Inventors: HUIMEI ZHOU, MIAOMIAO WANG, Nicolas Jean Loubet
  • Patent number: 11789064
    Abstract: A ring oscillator circuit design includes three or more inverter stages connected in series. Each inverter stage includes one or more inverter devices including a PMOS device and a coupled NMOS device. The PMOS device in each of odd alternating inverter devices of the three or more inverter stages having a source terminal receiving power from a power rail conductor, and a source terminal of the coupled NMOS device in each of first alternating inverter devices is grounded. An output of a last inverter device of a last stage of the three or more inverter stages is connected to an input of a first inverter stage. The method measures a first frequency of a first ring oscillator circuit and measures a second frequency of a second ring oscillator circuit design to determine either a BTI or HCI failure mechanism of the first ring oscillator circuit based on the measurements.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: October 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Huimei Zhou, Liqiao Qin, Miaomiao Wang, Effendi Leobandung
  • Publication number: 20230320056
    Abstract: Embodiments of present invention provide a static random-access-memory (SRAM) device. The SRAM device includes a first set of nanosheets used in an n-type transistor; and a second set of nanosheets with one or more nanosheets of the second set of nanosheets used in a p-type transistor, wherein a width of the second set of nanosheets is wider than a width of the first set of nanosheets. In one embodiment the p-type transistor is used as a pull-up transistor and the n-type transistor is used as a pull-down transistor or a pass-gate transistor. A method of manufacturing the SRAM device is also provided.
    Type: Application
    Filed: April 5, 2022
    Publication date: October 5, 2023
    Inventors: HUIMEI ZHOU, Carl Radens, MIAOMIAO WANG, Ardasheir Rahman
  • Publication number: 20230268271
    Abstract: Fabrication method for forming a resistance tunable fuse stack structure includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer, a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting at least one of the first and second fuse conductive layers. Selection of various attributes of the fuse stack structure tunes a resistance of a fuse formed between the first and second fuse contacts.
    Type: Application
    Filed: April 26, 2023
    Publication date: August 24, 2023
    Inventors: Alexander REZNICEK, Chih-Chao YANG, Miaomiao WANG, Donald CANAPERI
  • Patent number: 11694958
    Abstract: Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: July 4, 2023
    Assignee: International Business Machines Corporation
    Inventors: Huimei Zhou, Su Chen Fan, Miaomiao Wang, Zuoguang Liu
  • Publication number: 20230207622
    Abstract: Vertically stacked, buried power rails are electrically connected to wrap-around contacts or other electrically conductive liners on transistor source/drain regions. The buried power rails are electrically isolated from each other by an electrical insulator. Wrap-around contacts can be electrically connected to different ones of the vertically stacked, buried power rails or to the same buried power rail.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: HUIMEI ZHOU, Ruilong Xie, Julien Frougier, MIAOMIAO WANG
  • Publication number: 20230197813
    Abstract: A semiconductor structure comprises a first nanosheet device having at least one first channel layer and a first gate, a second nanosheet device disposed above the first nanosheet device and having at least one second channel layer and a second gate, and an isolation layer disposed between the first nanosheet device and the second nanosheet device to electrically isolate the first nanosheet device and the second nanosheet device.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Inventors: Huimei Zhou, Ruilong Xie, Miaomiao Wang, Alexander Reznicek
  • Publication number: 20230187514
    Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment of the invention, a GAA nanosheet device is formed in a first region of a substrate. The GAA nanosheet device includes a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack. A comb-nanosheet device is formed in a second region of a substrate. The comb-nanosheet device includes a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack that is less than the first fin spacing distance.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Inventors: Huimei Zhou, Julien Frougier, Nicolas Loubet, Ruilong Xie, Miaomiao Wang, Veeraraghavan S. Basker
  • Publication number: 20230187533
    Abstract: Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 15, 2023
    Inventors: Huimei Zhou, Kangguo Cheng, Su Chen Fan, Miaomiao Wang
  • Patent number: 11676894
    Abstract: A semiconductor structure includes a resistance tunable fuse stack structure. A fabrication method for forming the same includes forming on a substrate layer a first fuse conductive layer, directly on, and contacting a top surface of, the substrate layer, followed by forming a first inter-layer dielectric (ILD) layer, directly on, and contacting a top surface of, the first fuse conductive layer. The method forms a second fuse conductive layer, directly on, and contacting a top surface of, the first ILD layer, followed by forming a second ILD layer, directly on, and contacting a top surface of, the second fuse conductive layer, the layers are interleaved in a stack forming a fuse stack structure. First and second fuse contacts are formed in the fuse stack structure vertically extending through the layers and contacting the first and second fuse conductive layers.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: June 13, 2023
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Chih-Chao Yang, Miaomiao Wang, Donald Francis Canaperi
  • Publication number: 20230175921
    Abstract: A device and a method for determining a microvibration effect on a millisecond-level space optical sensor are provided. The device includes: a light source, a star simulator, an air flotation vibration isolation platform, a suspension system/air flotation system, a zero stiffness system, a supporting system, a six-degree-of-freedom microvibration simulator, a signal driving apparatus, and a data acquisition and processing system. In the device for determining a microvibration effect on a space pointing measurement apparatus, a free boundary condition and a zero gravity environment are simulated by using a suspension system and a zero stiffness system. A light source and a star simulator simulate a star at infinity. A six-degree-of-freedom microvibration simulator simulates an on-orbit microvibration mechanical environment which is used as an input of a test. Extremely high-precision sensors collect system response data.
    Type: Application
    Filed: June 24, 2021
    Publication date: June 8, 2023
    Applicant: BEIJING INSTITUTE OF CONTROL ENGINEERING
    Inventors: Li YUAN, Li WANG, Lin LI, Ran ZHENG, Yanpeng WU, Jun ZHONG, Jie SUI, Yuming LI, Miaomiao WANG, Huiyan CHENG, Xiaoyan WANG
  • Publication number: 20230160944
    Abstract: Reliability test macros for contact over active gate (COAG) layout designs are provided. In one aspect, a COAG layout design reliability test macro includes: gate-shaped dielectric structures disposed over an active area of a substrate; source/drain regions present on opposite sides of the gate-shaped dielectric structures; source/drain contacts in direct contact with the source/drain regions; a dielectric fill material disposed on the source/drain contacts; and gate contacts present over, and in direct contact with, the gate-shaped dielectric structures in the active area, wherein the dielectric fill material is present in between the gate contacts and the source/drain contacts. Methods of forming and using the present COAG layout design reliability test macros are also provided.
    Type: Application
    Filed: November 24, 2021
    Publication date: May 25, 2023
    Inventors: Huimei ZHOU, Ruilong XIE, Miaomiao WANG
  • Publication number: 20230117743
    Abstract: A self-aligned buried power rail having an adjustable height is formed between a first semiconductor device region and a second semiconductor device region. The self-aligned buried power rail having the adjustable height has improved conductivity. Notably, the self-aligned buried power rail has a first portion having a first height that is present in a gate cut trench and a second portion having a second height, which is greater than the first height, that is present in a source/drain cut trench.
    Type: Application
    Filed: October 20, 2021
    Publication date: April 20, 2023
    Inventors: HUIMEI ZHOU, Huiming Bu, MIAOMIAO WANG, Ruilong Xie
  • Publication number: 20230110825
    Abstract: In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.
    Type: Application
    Filed: September 27, 2021
    Publication date: April 13, 2023
    Inventors: Huimei Zhou, Julien Frougier, Xuefeng Liu, Jingyun Zhang, Lan Yu, Heng Wu, Miaomiao Wang, Veeraraghavan S. Basker
  • Publication number: 20230103999
    Abstract: A CFET (complementary field effect transistor) structure including a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, a first source/drain contact for the first source/drain region, and a second source drain contact for the second source drain region. The first source/drain contact is isolated from the second source/drain contact by an L-shaped isolation element including vertical and horizontal isolation elements.
    Type: Application
    Filed: October 5, 2021
    Publication date: April 6, 2023
    Inventors: HUIMEI ZHOU, Alexander Reznicek, MIAOMIAO WANG, Ruilong Xie