Patents by Inventor Michael A. Guillorn

Michael A. Guillorn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200251568
    Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
    Type: Application
    Filed: January 16, 2020
    Publication date: August 6, 2020
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence Hook, Robert R. Robison, Reinaldo Vega, Tenko Yamashita
  • Patent number: 10706200
    Abstract: A method for generating physical design layout patterns includes selecting as training data one or more physical design layout patterns of integrated multi-layers for features in at least two layers of a given patterned structure. The method also includes converting the physical design layout patterns into three-dimensional arrays, a given three-dimensional array comprising a set of two-dimensional arrays each representing features of one layer of the layers in a given one of the physical design layout patterns. The method further includes training, utilizing the three-dimensional arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating synthetic three-dimensional arrays utilizing the generator neural network of the trained GAN, a given synthetic three-dimensional array comprising a set of two-dimensional arrays each representing features for a new layer of a new physical design layout pattern.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jing Sha, Michael A. Guillorn, Martin Burkhardt, Derren N. Dunn
  • Patent number: 10699955
    Abstract: In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a first BOX layer and a second BOX layer, and an active layer over the second BOX layer; forming at least one STI region in the active layer having an STI oxide; forming at least one trench that extends through the STI oxide and the second BOX layer down to the seed layer, wherein the trench has a footprint and a location such that a portion of the STI oxide remains lining sidewalls of the trench; and growing an epitaxial material in the trench using the seed layer as a template for the growth, wherein the epitaxial material is doped and serves as the local interconnect structure which is buried in the double BOX SOI wafer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 30, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 10699055
    Abstract: A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of features in a given layer of a given patterned structure and converting the physical design layout patterns into two-dimensional (2D) arrays comprising entries for different locations in the given layer of the given patterned structure with values representing presence of the features at the different locations. The method also includes training, utilizing the 2D arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating one or more synthetic 2D arrays utilizing the trained generator neural network of the GAN, a given synthetic 2D array comprising entries for different locations in the given layer of a new physical design layout pattern with values representing presence of the features at the different locations of the new physical design layout pattern.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jing Sha, Michael A. Guillorn, Martin Burkhardt, Derren N. Dunn
  • Patent number: 10680061
    Abstract: Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Spacers are formed, with at least one top pair of spacers being positioned above an uppermost channel layer. The top pair of spacers each has a curved lower portion with a curved surface in contact with the gate stack and a straight upper portion that extends vertically from the curved portion along a straight sidewall of the gate stack.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Publication number: 20200159983
    Abstract: A computer-implemented method, computer program product, a computer processing system are provided for generating synthetic via layout patterns by a Recurrent Neural Network (RNN). The method includes generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts. The method further includes training, by the processor, the RNN with the training data set of coordinate arrays. The method also includes generating, by the processor, using the RNN, new synthetic via patterns.
    Type: Application
    Filed: January 22, 2020
    Publication date: May 21, 2020
    Inventors: Jing Sha, Michael A. Guillorn, Derren N. Dunn
  • Patent number: 10658461
    Abstract: Methods for forming field effect transistors include forming a stack of nanowires of alternating layers of channel material and sacrificial material, with a top layer of the sacrificial material forming a top layer of the stack. A dummy gate is formed over the stack. Channel material and sacrificial material of the stack of nanowires is etched away outside of a region covered by the dummy gate. The sacrificial material is then selectively etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. The dummy gate is etched away with an anisotropic etch. The sacrificial material is etched away to expose the layers of the channel material. A gate stack is formed over and around the layers of the channel material.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 19, 2020
    Assignee: Tessera, Inc.
    Inventors: Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10650111
    Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Daniel Corliss, Derren N. Dunn, Michael A. Guillorn, Shawn P. Fetterolf
  • Publication number: 20200143098
    Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.
    Type: Application
    Filed: January 2, 2020
    Publication date: May 7, 2020
    Inventors: Daniel Corliss, Derren N. Dunn, Michael A. Guillorn, Shawn P. Fetterolf
  • Publication number: 20200134251
    Abstract: A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising expanding a shape of the guiding pattern by a predetermined distance in both lateral directions to form a fin keep mask, where the fin keep mask comprises a stand-alone mask
    Type: Application
    Filed: December 30, 2019
    Publication date: April 30, 2020
    Inventors: Michael A. Guillorn, Kafai Lai, Chi-Chun Liu, Ananthan Raghunathan, Hsinyu Tsai
  • Patent number: 10621302
    Abstract: Methods and systems for fabricating an integrated circuit include training a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot. It is determined whether an input physical design layout pattern includes a hotspot using the machine learning model. A hotspot localization is generated for the input physical design layout patterns. The input physical design pattern is adjusted to cure the hotspot. A circuit is fabricated in accordance with the adjusted input physical design layout pattern.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jing Sha, Dongbing Shao, Martin Burkhardt, Michael A. Guillorn
  • Patent number: 10621301
    Abstract: A method is presented for generating a plurality of physical design layout patterns. The method includes selecting one or more physical design layouts for neural network training, converting the plurality of physical design layout patterns into coordinate arrays, a coordinate array of the coordinate arrays including via center coordinates of vias in a physical design layout pattern of the plurality of physical design layout patterns, training, by employing the coordinate arrays, a variational autoencoder (VAE), and generating one or more new synthetic coordinate arrays by employing the trained VAE, a synthetic coordinate array of the one or more new synthetic coordinate arrays including via center coordinates of vias for a new physical design layout pattern.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jing Sha, Michael A. Guillorn, Derren N. Dunn
  • Patent number: 10615281
    Abstract: A semiconductor device includes a plurality of semiconductor layers formed on a plurality of fin structures, an epitaxial layer formed on the plurality of fin structures and on a sidewall of the plurality of semiconductor layers, a gate structure formed on the plurality of semiconductor layers, and a wrap around contact formed on the epitaxial layer.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Nicolas Jean Loubet
  • Patent number: 10606980
    Abstract: A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising: inserting a first external dummy along an external edge of the guiding pattern in a vertical direction; and inserting a second external dummy at a fixed distance from a second edge of the first external dummy, wherein the second external dummy includes a two-dimensional shape such that at least two edges of the second external dummy are parallel to the second edge of the first external dummy.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Kafai Lai, Chi-Chun Liu, Ananthan Raghunathan, Hsinyu Tsai
  • Patent number: 10606975
    Abstract: A method for generating physical design layout patterns includes the step of selecting one or more physical design layouts, a given physical design layout comprising a set of physical design layout patterns for features in at least one layer of a given patterned structure. The method also includes the step of converting the physical design layout patterns into coordinate arrays, a given coordinate array comprising feature center coordinates for the features in a given one of the physical design layout patterns. The method further includes the step of training, utilizing the coordinate arrays, a generative adversarial network (GAN) comprising discriminator and generator neural networks. The method further includes the step of generating one or more synthetic coordinate arrays utilizing the trained generator neural network of the GAN, a given one of the synthetic coordinate arrays comprising feature center coordinates of features for a new physical design layout pattern.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jing Sha, Michael A. Guillorn, Derren N. Dunn
  • Publication number: 20200098893
    Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 26, 2020
    Inventors: Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • Patent number: 10600680
    Abstract: A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a dielectric layer. The neutral layer is composed of a neutral charged di-block polymer. Patterning the neutral layer, the hardmask layer and the dielectric layer to provide openings that are filled with a metal material to provide metal features. A self-assembled di-block copolymer material is deposited on a patterned surface of the neutral layer and the metal features. The self-assembled di-block copolymer material includes a first block composition with a first affinity for alignment to the metal features. The first block composition of the self-assembled di-block copolymer is converted to a metal that is self-aligned to the metal features.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Markus Brink, Michael A. Guillorn, Chung-Hsun Lin, HsinYu Tsai
  • Patent number: 10599807
    Abstract: A computer-implemented method, computer program product, a computer processing system are provided for generating synthetic via layout patterns by a Recurrent Neural Network (RNN). The method includes generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts for a set of integrated circuit elements. The method further includes training, by the processor, the RNN with the training data set of coordinate arrays. The method also includes generating, by the processor, using the RNN, new synthetic via patterns.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jing Sha, Michael A. Guillorn, Derren N. Dunn
  • Publication number: 20200091289
    Abstract: Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10592635
    Abstract: A computer-implemented method, computer program product, and computer processing system are provided for generating synthetic layout patterns. The method includes receiving, by a processor, a set of physical design layouts that include a variety of layout patterns for neural network training. The method further includes generating, by the processor, a set of training layout pattern images for the neural network training by performing automatic image capturing on the set of physical design layouts with scripts. The method also includes training, by the processor, a feedforward neural network (FFNN)-based Variational Autoencoder (VAE) with the set of training layout pattern images. The method additionally includes generating, by the processor using the FFNN-based VAE, new synthetic layout images.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jing Sha, Michael A. Guillorn, Derren N. Dunn