Abstract: A lifting framework for an industrial truck has an extendible mast guided on a guide mast by rollers. Means are provided for bracing the extendible mast with the guide mast so as to prevent the extendible mast from inclining in the lateral direction of the lifting framework relative to the guide mast. The bracing means are configured such that, when the extendible mast is located in the top end position, a vertical movement of the extendible mast relative to the guide mast is prevented in the region of each of the two columns. A hydraulic lifting cylinder and a stop for the top end position of the extendible mast are arranged here in the region of each column.

Abstract: Various structures chip packages are disclosed including a magnetoresistive random access memory (“MRAM”) device and a magnetic shield structure. The magnetic shield structure may be made from material having either ferromagnetic or diamagnetic material and may be shaped and incorporated into the chip package to divert stray magnetic fields away from the MRAM device.

Abstract: A stackable chip assembly is disclosed, as are many different embodiments relating to same. The chip assembly preferably includes at least two substrates with components mounted on each. The substrates are preferably situated with respect to one another such that components on one substrate extend towards the other substrate and vice versa. The components of each substrate preferably extend between each other. In addition various connections between the substrates are disclosed, as well as methods of constructing such chip assemblies.

Abstract: A packaged semiconductor chip includes features such as a chip carrier having a large thermal conductor which can be solder-bonded to a circuit panel so as to provide enhanced thermal conductivity to the circuit panel and electromagnetic shielding and a conductive enclosure which partially or completely surrounds the packaged chip to provide additional heat dissipation and shielding. The packaged unit may include both an active semiconductor chip and a passive element, desirably in the form of a chip, which includes resistors and capacitors. Inductors may be provided in whole or in part on the chip carrier.

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Abstract: A dielectric structure is formed by a molding process, so that a first surface of a dielectric structure is shaped by contact with the mold. The opposite second surface of the dielectric structure is applied onto the front surface of a wafer element. The dielectric layer may include protruding bumps and terminals may be formed on the bumps. The bumps may be of a precise height. The terminals lie at a precisely controlled height above the front surface of the wafer element. The terminals may include projecting posts which extend above a surrounding solder mask layer to facilitate engagement with a test fixture. The posts are immersed within solder joints when the structure is bonded to a circuit panel.

Abstract: A stackable chip assembly is disclosed, as are different embodiments relating to same. The chip assembly preferably includes at least two substrates with components mounted on each. The substrates are preferably situated with respect to one another such that components on one substrate extend towards the other substrate and vice versa. The components of each substrate preferably extend or are interspersed between each other. Different connections between the substrates are disclosed, as well as methods of constructing such chip assemblies. In addition, a high G-force testing fixture is also disclosed for use in testing chip packages or the like.

Abstract: A packaged microelectronic device is provided which includes: (a) a unit having a chip with an upwardly-facing front surface and a downwardly-facing rear surface, a lid overlying at least a portion of the front surface of the chip, the lid having a top surface facing upwardly away from the chip and unit connections exposed at the top surface of the lid. At least some of the unit connections are electrically connected to the chip. The packaged microelectronic device also includes a package structure including structure defining package terminals, at least some of the package terminals being electrically connected to the chip. The package structure, the unit or both define a downwardly-facing bottom surface of the package, the terminals being exposed at the bottom surface.

Abstract: A radio frequency chip package is formed by assembling a connecting element such as a circuit board or flexible circuit tape having chips thereon with a bottom plane element such as a lead frame incorporating a large thermally-conductive plate and leads projecting upwardly from the plane of the plate. The assembly step places the rear surfaces of the chips on the bottom side of the connecting element into proximity with the thermal conductor and joins the conductive traces on the connecting element with the leads. The resulting assembly is encapsulated, leaving terminals at the bottom ends of the leads exposed. The encapsulated assembly may be surface-mounted to a circuit board. The leads provide robust electrical connections between the connecting element and the circuit board.

Abstract: A packaged microelectronic device is provided which includes: (a) a unit having a chip with an upwardly-facing front surface and a downwardly-facing rear surface, a lid overlying at least a portion of the front surface of the chip, the lid having a top surface facing upwardly away from the chip and unit connections exposed at the top surface of the lid. At least some of the unit connections are electrically connected to the chip. The packaged microelectronic device also includes a package structure including structure defining package terminals, at least some of the package terminals being electrically connected to the chip. The package structure, the unit or both define a downwardly-facing bottom surface of the package, the terminals being exposed at the bottom surface.

Abstract: A radio frequency chip package is formed by assembling a connecting element such as a circuit board or flexible circuit tape having chips thereon with a bottom plane element such as a lead frame incorporating a large thermally-conductive plate and leads projecting upwardly from the plane of the plate. The assembly step places the rear surfaces of the chips on the bottom side of the connecting element into proximity with the thermal conductor and joins the conductive traces on the connecting element with the leads. The resulting assembly is encapsulated, leaving terminals at the bottom ends of the leads exposed. The encapsulated assembly may be surface-mounted to a circuit board. The leads provide robust electrical connections between the connecting element and the circuit board.

Abstract: A stacked microelectronic assembly includes a plurality of microelectronic subassemblies. Each subassembly includes a substrate having at least one site, a plurality of first contacts and a plurality of second contacts. Each subassembly also has at least one microelectronic element assembled to the at least one attachment site and electrically connected to at least some of the first and second contacts. The substrate is folded so that the first contacts are accessible at a bottom of a subassembly and the second contacts are accessible at a top of a subassembly. The plurality of subassemblies are stacked one on top of another in a generally vertical configuration. The substrate of at least one of the subassemblies has a plurality of attachment sites and a plurality of microelectronic elements assembled to the attachment sites. The substrate is folded so that at least some of the plurality of microelectronic elements are disposed alongside one another.

Abstract: A microelectronic assembly includes a first microelectronic element having a first face and contacts accessible at the first face, and a layer of a dielectric material having a bottom surface contacting the first microelectronic element, a top surface facing away from the first microelectronic element and holes extending between the top and bottom faces in alignment with the contacts on the first microelectronic element. The assembly includes conductive protrusions extending through the holes to the contacts, the conductive protrusions projecting beyond the top surface of the dielectric layer.

Abstract: An apparatus for elastic hysteretic palpatory training includes a wire or a computer controlled actuator having a plunger that at least partially elastically resists the application of a palpatory force. In use of the apparatus, an increasing palpatory force is applied to an end of the wire transverse to its axis or an end of the plunger of the actuator in a first direction. In response to the applied palpatory force, the wire or the plunger elastically resist displacement from a first position to a second position. The palpatory force is then withdrawn whereupon the elasticity of wire or the elasticity emulated by the plunger causes it to return toward the first position. The applied palpatory force versus displacement is detected in response to applying and withdrawing the palpatory force to the wire or the plunger.

Abstract: A method is disclosed for making a microelectronic package. A material is applied to a first major surface of a microelectronic element to reduce the heights of protrusions projecting from the first major surface. The microelectronic element is assembled to a microelectronic component. A method of forming protrusions and an assembly incorporating the microelectronic element having protrusions is also disclosed.

Abstract: A method to project staffing needs may include predetermining an optimal prediction method for predicting staffing needs from a plurality of prediction methods based on at least one of a center, a target day in a forecasting horizon and a time interval using historical data. The method may also include predicting future staffing needs for at least one of a selected center, a selected target day and a selected time interval by using the predetermined optimal prediction method for the at least one of selected center, selected target day and selected time interval.

Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.

Abstract: Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap bearing the inductive element, and this flap may be bent to tilt the inductive element out of the plane of the chip carrier to reduce electromagnetic interaction between the inductive element and surrounding electrical components. Other inductors include solenoids formed in part by leads on the chip carrier as, for example, by displacing leads out of the plane of the chip carrier to form loops in vertically-extensive planes transverse to the plane of the chip carrier. Additional features provide trimming of the inductor to a desired inductance value during by breaking or connecting leads during assembly.

Abstract: A microelectronic subassembly includes a substrate having a first surface, and one or more microelectronic elements positioned above the first surface of the substrate, each microelectronic element having a contact bearing face confronting the first surface of the substrate and a back surface remote therefrom. The subassembly includes a substantially rigid plate attached to the back surfaces of the microelectronic elements, an array of flexible leads extending between the substrate and the microelectronic elements, the leads having first ends attached to the substrate and second ends attached to the contacts of the microelectronic elements, and an at least partially cured spacer material sandwiched between the substantially rigid plate and the substrate for holding the contact bearing faces of the microelectronic elements at a precise height above the substrate.

Abstract: Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap bearing the inductive element, and this flap may be bent to tilt the inductive element out of the plane of the chip carrier to reduce electromagnetic interaction between the inductive element and surrounding electrical components. Other inductors include solenoids formed in part by leads on the chip carrier as, for example, by displacing leads out of the plane of the chip carrier to form loops in vertically-extensive planes transverse to the plane of the chip carrier. Additional features provide trimming of the inductor to a desired inductance value during by breaking or connecting leads during assembly.