Patents by Inventor Michael Beck

Michael Beck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100054022
    Abstract: In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.
    Type: Application
    Filed: August 29, 2008
    Publication date: March 4, 2010
    Applicants: QIMONDA AG, INFINEON TECHNOLOGIES AG
    Inventors: Michael Beck, Martin Kerber, Peter Lahnor, Roland Thewes
  • Patent number: 7670497
    Abstract: A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: March 2, 2010
    Assignees: International Business Machines Corporation, Infineon Technologies AG
    Inventors: John A. Fitzsimmons, David L. Rath, Shom Ponoth, Michael Beck
  • Publication number: 20100041257
    Abstract: An electrical connector including a receptacle having receptacle having at least one shielding member and at least one electrically conductive surface. The shielding member includes at least one grounding member and at least one latching member. The grounding member is in physical contact with the electrically conductive surface and the latching member is configured to detachably engage a latching feature of a mating receptacle. A connector system and a method for shielding a connector are also disclosed.
    Type: Application
    Filed: August 14, 2008
    Publication date: February 18, 2010
    Applicant: TYCO ELECTRONICS CORPORATION
    Inventors: Timothy Michael BECK, Michael Scott FEHER, Edward J. HOWARD, Navin Kanjibhai PATEL
  • Patent number: 7651942
    Abstract: A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive region and the trench. A sacrificial liner to release organic residues is deposited in the via and over the upper surface of the wafer, over which an organic planarization layer is deposited. The organic planarization layer is removed with a dry plasma etch, followed by a wet clean to remove the sacrificial liner. A diffusion barrier to separate the conductive material from the dielectric layers is deposited over the dual damascene structure and over the upper surface of the wafer. A conductive structure is formed over the diffusion barrier and polished to form an even surface for further processing steps.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: January 26, 2010
    Assignee: Infineon Technologies AG
    Inventors: Frank Huebinger, Michael Beck
  • Publication number: 20100013104
    Abstract: An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.
    Type: Application
    Filed: September 25, 2009
    Publication date: January 21, 2010
    Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INFINEON TECHNOLOGIES NORTH AMERICA CORP., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wuping Liu, Michael Beck, John A. Fitzsimmons
  • Patent number: 7615484
    Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: November 10, 2009
    Assignees: Chartered Semiconductor Manufacturing Ltd., Infineon Technologies North America Corp., International Business Machines Corporation
    Inventors: Wuping Liu, Michael Beck, John A. Fitzsimmons
  • Publication number: 20090247551
    Abstract: The present invention relates to novel substituted enaminocarbonyl compounds, to processes for their preparation and to their use for controlling animal pests, especially arthropods, in particular insects.
    Type: Application
    Filed: March 19, 2007
    Publication date: October 1, 2009
    Applicant: Bayer CropScience AG
    Inventors: Peter Jeschke, Robert Velten, Thomas Schenke, Otto Schallner, Michael Beck, Olga Malsam, Ralf Nauen, Ulrich Görgens, Thomas Müller, Christian Arnold, Erich Sanwald
  • Publication number: 20090221596
    Abstract: The invention relates to compounds of the formula (I) in which A1, A2, R1, R2, R3, R4, R5 and X are as defined in the description, to processes and intermediates for their preparation, and to their use for controlling pests.
    Type: Application
    Filed: May 6, 2006
    Publication date: September 3, 2009
    Inventors: Iris Escher, Michael Müller, Peter Jeschke, Michael Beck, Oliver Gaertzen, Olga Malsam, Peter Lösel, Ulrich Ebbinghaus-Kintscher, Christian Arnold, Karl-Josef Haack
  • Publication number: 20090194850
    Abstract: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 6, 2009
    Inventors: Erdem Kaltalioglu, Michael Beck
  • Publication number: 20090130148
    Abstract: The present invention relates to new attenuated M. bovis bacteria strains. Moreover, the present invention also provides immunogenic compositions comprising live bacteria of an of those attenuated M. bovis bacteria strain, their manufacture and use for the treatment and prophylaxis of M. bovis infections.
    Type: Application
    Filed: October 29, 2008
    Publication date: May 21, 2009
    Applicant: Boehringer Ingelheim Vetmedica, Inc.
    Inventors: Michael Beck, Jeffrey Knittel
  • Patent number: 7515399
    Abstract: In order to render possible a compact means for power distribution and fuse protection on the basis of a printed circuit board, the apparatus has a multiple fuse arrangement which comprises a plurality of fuses and is connected to a plurality of output contacts. Furthermore, a printed circuit board is provided, which has a feed plate, which is connected to the multiple fuse arrangement, in particular by means of plug-in contact elements, arranged on one of its sides. The output contacts are arranged on that side of the printed circuit board which is opposite the feed plate.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: April 7, 2009
    Assignee: Leoni Bordnetz-Systeme GmbH
    Inventors: Stephan Kriegesmann, Michael Beck, Hermann Bommersheim, Volker Helbig, Alfred Sadrinna, Gregor Storsberg
  • Publication number: 20090008361
    Abstract: A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure.
    Type: Application
    Filed: July 6, 2007
    Publication date: January 8, 2009
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORP.
    Inventors: John A. Fitzsimmons, David L. Rath, Shom Ponoth, Michael Beck
  • Publication number: 20080293935
    Abstract: The present invention is directed towards a method for the production of 2,4,6-trimercapto-1,3,5-triazine (TMT-H3). In particular, the method of the subject matter relates to the operation of acidifying the salts of 2,4,6-trimercapto-1,3,5-triazine in aqueous solution and in a defined pH range.
    Type: Application
    Filed: July 3, 2006
    Publication date: November 27, 2008
    Applicant: Evonik Degussa GmbH
    Inventors: Peter Werle, Martin Trageser, Michael Beck
  • Patent number: 7452804
    Abstract: In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: November 18, 2008
    Assignee: Infineon Technologies AG
    Inventors: Michael Beck, Bee Kim Hong, Armin Tilke, Hermann Wendt
  • Publication number: 20080265409
    Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.
    Type: Application
    Filed: April 24, 2007
    Publication date: October 30, 2008
    Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., INFINEON TECHNOLOGIES NORTH AMERICA CORP., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wuping Liu, Michael Beck, John A. Fitzsimmons
  • Patent number: 7417150
    Abstract: The present application relates to novel heterocyclic compounds, to processes for their preparation, and to their use as crop protection agents, particularly for controlling animal pests.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: August 26, 2008
    Assignee: Bayer CropScience AG
    Inventors: Peter Jeschke, Michael Beck, Wolfgang Krämer, Detlef Wollweber, Angelika Lubos-Erdelen, legal representative, Andreas Turberg, Olaf Hansen, Hans-Dieter Martin, Piet Sauer, Christoph Erdelen
  • Publication number: 20080070404
    Abstract: Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The method includes patterning the material layer partially with a first pattern, and patterning the material layer partially with a second pattern. Patterning the material layer partially with the second pattern further comprises simultaneously completely patterning the material layer with the first pattern.
    Type: Application
    Filed: September 19, 2006
    Publication date: March 20, 2008
    Inventors: Michael Beck, Erdem Kaltalioglu
  • Patent number: 7332428
    Abstract: In a method of fabricating a semiconductor device, a dielectric layer is formed over a conductive region. A dual damascene structure including a trench and a via is formed within the dielectric layer. A liner is formed over the dual damascene structure. The liner is selectively removed from above the upper surface of the conductive region to expose the upper surface of the conductive region. After the selectively removing process, at least a portion of the liner remains over the lower surface of the trench and the sidewalls of the trench and the via hole. A wet etch can then be performed to etch a recess in the conductive region. A conductive material is then formed within the damascene structure. This conductive material physically contacts the conductive region and is separated from the dielectric layer by the remaining portion of the liner.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: February 19, 2008
    Assignee: Infineon Technologies AG
    Inventor: Michael Beck
  • Publication number: 20070277425
    Abstract: An apparatus to capture snakes or small animals has an inner extensible coil spring support structure having shape memory. The support structure is overlaid or enclosed by a flexible mesh netting having open spaces whereby the snakes may pass through the spaces only when moving in a first forward direction. A deployment container houses the support structure and the netting when the support structure is in a retracted position. Multiple layers of concentrically arranged netting with different mesh sizes may be used to enclose the support structure.
    Type: Application
    Filed: May 14, 2007
    Publication date: December 6, 2007
    Inventor: Michael Beck
  • Publication number: 20070263344
    Abstract: In order to render possible a compact means for power distribution and fuse protection on the basis of a printed circuit board, the apparatus has a multiple fuse arrangement (10) which comprises a plurality of fuses (14) and is connected to a plurality of output contacts (18). Furthermore, a printed circuit board (2) is provided, which has a feed plate (4), which is connected to the multiple fuse arrangement (10), in particular by means of plug-in contact elements (8), arranged on one of its sides. The output contacts (18) are arranged on that side of the printed circuit board (2) which is opposite the feed plate (4).
    Type: Application
    Filed: March 2, 2007
    Publication date: November 15, 2007
    Inventors: Stephan Kriegesmann, Michael Beck, Hermann Bommersheim, Volker Helbig, Alfred Sadrinna, Gregor Storsberg