Abstract: An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.

Abstract: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

Abstract: In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

Abstract: The present invention relates to new attenuated M. bovis bacteria strains passaged at least 110 times. Moreover, the present invention also provides immunogenic compositions comprising live bacteria of any of those attenuated M. bovis bacteria strain, their manufacture and use for the treatment and prophylaxis of M. bovis infections and combinations with other veterinary vaccines or medicaments.

Abstract: A system (1), a method and an operating unit (62) for the creation of mixed layers for pallets (81, 82, 83, 84) are disclosed. A storage (10) is provided in which at least two different pack types are stored on a plurality of pallets (81, 82, 83, 84), including a plurality of layers of homogenous packs. The packs are intermediately stored in a plurality of individual, parallel conveyors (301, 302, . . . 30N) in a homogenous state. Based on the input of a user (5) on a touch panel (62), the packs are supplied to a grouping table (50) via a supply conveyor (40) in a predetermined sequence. A controller (60) is associated with the system (1) so that, in the grouping table (50), individual different pack types are allocated to the predefined positions of the different pack types as a function of predefined positions of the different pack types in a layer pattern (14) of a layer (24) of a production pallet (12).

Abstract: A computer system and a method for calculating an ADME properties of a substance on the basis of molecular properties of the substance by using a biophysical model, into which the molecular properties are entered as input quantities. The biophysical model establishes a relationship between the molecular properties and the ADME properties.

Abstract: The present invention relates to a transformer with a coil body accommodating at least one primary coil and one secondary coil. It is the object of the present invention to provide a transformer which, using the smallest possible amount of high-grade insulation material, ensures good insulation while remaining compact and easily assembled. The object is achieved by a transformer of the above type which is characterized in that the coil body comprises at least one primary part, accommodating the primary coil, and one secondary part, accommodating the secondary coil, and wherein at least one section of the primary part can be covered by at least one section of the secondary part. This section of the secondary part performs the function of the fire-protection housing for the primary part of the transformer.

Abstract: One implementation is a method for fabricating a semiconductor on a substrate. A first layer is formed on the substrate. An implanted pattern is introduced into the first layer by implanting using a structured implantation mask arranged over the first layer. A structured second layer is formed on the first layer after removing the implantation mask. A first pattern is generated in the substrate using the second layer as a mask. The first layer is developed with regard to the implanted pattern. A second pattern is generated in the substrate using the first layer as a mask.

Abstract: Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (?2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.

Abstract: The present invention relates to a power supply circuit comprising at least one transformer which is connected to a primary side circuit and to a secondary side circuit. The present invention further relates to a method for producing such a power supply circuit. To provide an improved power supply circuit which has a reduced size and increased power density and offers more flexibility in the formation of the safety distances between primary side and secondary side, the primary side circuit and the secondary side circuit are each mounted on at least one separate circuit carrier, said circuit carriers being mechanically and electrically coupled to one another and arranged in at least two different planes. According to advantageous embodiments, said circuit carriers may be arranged in planes that are either parallel with or transverse to one another.

Abstract: In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

Abstract: A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure.

Abstract: An electrical connector including a receptacle having receptacle having at least one shielding member and at least one electrically conductive surface. The shielding member includes at least one grounding member and at least one latching member. The grounding member is in physical contact with the electrically conductive surface and the latching member is configured to detachably engage a latching feature of a mating receptacle. A connector system and a method for shielding a connector are also disclosed.

Abstract: A method of fabricating a semiconductor device including a metal interconnect structure with a conductive region formed in a first dielectric layer, and an overlying, low-k, dielectric layer. A via and trench are formed in a dual damascene structure in the overlying dielectric layer, the via aligned with the conductive region and the trench. A sacrificial liner to release organic residues is deposited in the via and over the upper surface of the wafer, over which an organic planarization layer is deposited. The organic planarization layer is removed with a dry plasma etch, followed by a wet clean to remove the sacrificial liner. A diffusion barrier to separate the conductive material from the dielectric layers is deposited over the dual damascene structure and over the upper surface of the wafer. A conductive structure is formed over the diffusion barrier and polished to form an even surface for further processing steps.

Abstract: An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening.

Abstract: An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

Abstract: The present invention relates to novel substituted enaminocarbonyl compounds, to processes for their preparation and to their use for controlling animal pests, especially arthropods, in particular insects.

Abstract: The invention relates to compounds of the formula (I) in which A1, A2, R1, R2, R3, R4, R5 and X are as defined in the description, to processes and intermediates for their preparation, and to their use for controlling pests.

Abstract: Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

Abstract: The present invention relates to new attenuated M. bovis bacteria strains. Moreover, the present invention also provides immunogenic compositions comprising live bacteria of an of those attenuated M. bovis bacteria strain, their manufacture and use for the treatment and prophylaxis of M. bovis infections.