Patents by Inventor Michael Goldsmith

Michael Goldsmith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240274252
    Abstract: A method of generating a dosage calculator for determining a dosage of a drug for administering to a patient, the method comprising: receiving population data comprising real population data, and/or simulated population data calculated using a pharmacokinetic-pharmacodynamic, PKPD, model for the drug; and training a machine learning dosage calculator using the population data.
    Type: Application
    Filed: October 5, 2023
    Publication date: August 15, 2024
    Applicant: Closed Loop Medicine Ltd.
    Inventors: Paul Goldsmith, Bruce Campbell, Michael Catt
  • Publication number: 20240220699
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed including at least one memory; machine-readable instructions; and processor circuitry to at least one of execute or instantiate the machine-readable instructions to: obtain a register-transfer level design defining operations of electrical circuits in first and second dice of a multi-die semiconductor package, the second die to be stacked on the first die in the multi-die semiconductor package; and select placement of a cell for a physical layout for the multi-die semiconductor package based on the register-transfer level design, the cell including a via to electrically interconnect the first die to the second die.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Inventors: Michael Goldsmith, Prashant Majhi, Per Sverdrup, Chung-Ching Peng
  • Patent number: 11995001
    Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Krystof C. Zmudzinski, Siddhartha Chhabra, Uday R. Savagaonkar, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Raghunandan Makaram, Carlos V. Rozas, Amy L. Santoni, Vincent R. Scarlata, Vedvyas Shanbhogue, Ilya Alexandrovich, Ittai Anati, Wesley H. Smith, Michael Goldsmith
  • Publication number: 20230042288
    Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
    Type: Application
    Filed: July 18, 2022
    Publication date: February 9, 2023
    Applicant: Intel Corporation
    Inventors: Krystof C. Zmudzinski, Siddhartha Chhabra, Uday R. Savagaonkar, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Raghunandan Makaram, Carlos V. Rozas, Amy L. Santoni, Vincent R. Scarlata, Vedvyas Shanbhogue, Ilya Alexandrovich, Ittai Anati, Wesley H. Smith, Michael Goldsmith
  • Publication number: 20220306640
    Abstract: A compound of formula (I-a): wherein the symbols are defined in the specification, and which has a strong DDR1 inhibitory activity, and can be a therapeutic agent for DDR1-related diseases, for example, a cancer, a kidney disease, a cardiovascular disease, a central nervous system disease, or fibrosis.
    Type: Application
    Filed: September 4, 2020
    Publication date: September 29, 2022
    Applicant: ONO PHARMACEUTICAL CO., LTD.
    Inventors: Yota NISHIOKA, Masakuni KURONO, Rena NISHIZAWA, Balachandra BANDODKAR, Xuechao GAO, Zhilong WAN, Ranran LV, Kevin DOYLE, Michael GOLDSMITH
  • Patent number: 11408160
    Abstract: Described is a resilient fluid control valve assembly. The resilient fluid control valve assembly includes a cartridge housing having an upper portion and a lower portion. The upper portion is formed to reside above a drain opening, while the lower portion is formed to reside within the drain opening. The resilient fluid control valve assembly further includes a resilient fluid control valve positioned within the cartridge housing. The resilient fluid control valve has a valve body portion and a sealing portion. When positioned within the cartridge housing, a portion of the valve body portion resides above the drain opening, and a portion of the sealing portion resides within the drain opening.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: August 9, 2022
    Inventor: Edward Michael Goldsmith
  • Patent number: 11392507
    Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Krystof C. Zmudzinski, Siddhartha Chhabra, Uday R. Savagaonkar, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Raghunandan Makaram, Carlos V. Rozas, Amy L. Santoni, Vincent R. Scarlata, Vedvyas Shanbhogue, Ilya Alexandrovich, Ittai Anati, Wesley H. Smith, Michael Goldsmith
  • Publication number: 20210255962
    Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
    Type: Application
    Filed: January 22, 2021
    Publication date: August 19, 2021
    Applicant: Intel Corporation
    Inventors: Krystof C. Zmudzinski, Siddhartha Chhabra, Uday R. Savagaonkar, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Raghunandan Makaram, Carlos V. Rozas, Amy L. Santoni, Vincent R. Scarlata, Vedvyas Shanbhogue, Ilya Alexandrovich, Ittai Anati, Wesley H. Smith, Michael Goldsmith
  • Patent number: 11023385
    Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: June 1, 2021
    Assignee: INTEL CORPORATION
    Inventors: Kiran S. Panesar, Michael A. Goldsmith
  • Patent number: 10975560
    Abstract: A hybrid flushing system for water free urinals is presented with a housing having a wall portion forming a cavity for receiving a cartridge. The housing also includes a flushing fluid inlet portion for receiving a flushing fluid and a flushing fluid directing portion configured to direct the flushing fluid. A cartridge for installation into a housing is presented, including a cartridge wall, a flushing fluid receiving portion and a flushing fluid directing portion to direct flushing fluid received to any portion to clean areas of the housing, the cartridge, and connected plumbing. Steps for cleaning a hybrid flushing system are presented with an act of directing a flushing fluid into an area, where the area is one of a cartridge for a hybrid flushing system, a housing for a hybrid flushing system, and a plumbing system connected with the hybrid flushing system.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: April 13, 2021
    Assignee: FALCON WATER TECHNOLOGIES, LLC
    Inventor: Edward Michael Goldsmith
  • Patent number: 10922241
    Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Krystof C. Zmudzinski, Siddhartha Chhabra, Uday R. Savagaonkar, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Raghunandan Makaram, Carlos V. Rozas, Amy L. Santoni, Vincent R. Scarlata, Vedvyas Shanbhogue, Ilya Alexandrovich, Ittai Anati, Wesley H. Smith, Michael Goldsmith
  • Patent number: 10885202
    Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Francis X. McKeen, Carlos V. Rozas, Uday R. Savagaonkar, Simon P. Johnson, Vincent Scarlata, Michael A. Goldsmith, Ernie Brickell, Jiang Tao Li, Howard C. Herbert, Prashant Dewan, Stephen J. Tolopka, Gilbert Neiger, David Durham, Gary Graunke, Bernard Lint, Don A. Van Dyke, Joseph Cihula, Stalinselvaraj Jeyasingh, Stephen R. Van Doren, Dion Rodgers, John Garney, Asher Altman
  • Publication number: 20200356490
    Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.
    Type: Application
    Filed: May 26, 2020
    Publication date: November 12, 2020
    Inventors: Kiran S. PANESAR, Michael A. GOLDSMITH
  • Publication number: 20200325667
    Abstract: Described is a resilient fluid control valve assembly. The resilient fluid control valve assembly includes a cartridge housing having an upper portion and a lower portion. The upper portion is formed to reside above a drain opening, while the lower portion is formed to reside within the drain opening. The resilient fluid control valve assembly further includes a resilient fluid control valve positioned within the cartridge housing. The resilient fluid control valve has a valve body portion and a sealing portion. When positioned within the cartridge housing, a portion of the valve body portion resides above the drain opening, and a portion of the sealing portion resides within the drain opening.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 15, 2020
    Inventor: Edward Michael Goldsmith
  • Patent number: 10671541
    Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Kiran S. Panesar, Michael A. Goldsmith
  • Patent number: 10597859
    Abstract: A device for the disposal of human waste matter, specifically a toilet, is presented. This toilet incorporates elements designed to prevent both a loss of flushing efficiency and an extensive consumption of water, all while improving upon the basic functionalities of the toilet as such. These elements include specialized parts designed to both improve the efficacy of the “siphon jet” type toilet by precluding the possibility of aeration within certain critical components of the toilet system proper, as well as a specialized rim fed channel whose intersection of the filled jet channel always travels below the operating water level of the bowl, and a vacuum assisted flushing system, whose primary purpose is to enhance the power of the toilet's flushing action.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: March 24, 2020
    Assignee: Falcon Waterfree Technologies, LLC
    Inventors: Philip Hennessy, Edward Michael Goldsmith
  • Patent number: 10592421
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Carlos V. Rozas, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael A. Goldsmith, Barry E. Huntley, Anton Ivanov, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Rinat Rappoport, Scott D. Rodgers, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, William C. Wood
  • Publication number: 20200063427
    Abstract: A hybrid flushing system for water free urinals is presented with a housing having a wall portion forming a cavity for receiving a cartridge. The housing also includes a flushing fluid inlet portion for receiving a flushing fluid and a flushing fluid directing portion configured to direct the flushing fluid. A cartridge for installation into a housing is presented, including a cartridge wall, a flushing fluid receiving portion and a flushing fluid directing portion to direct flushing fluid received to any portion to clean areas of the housing, the cartridge, and connected plumbing. Steps for cleaning a hybrid flushing system are presented with an act of directing a flushing fluid into an area, where the area is one of a cartridge for a hybrid flushing system, a housing for a hybrid flushing system, and a plumbing system connected with the hybrid flushing system.
    Type: Application
    Filed: April 29, 2019
    Publication date: February 27, 2020
    Inventor: Edward Michael Goldsmith
  • Publication number: 20190324918
    Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.
    Type: Application
    Filed: May 3, 2019
    Publication date: October 24, 2019
    Inventors: Krystof C. Zmudzinski, Siddhartha Chhabra, Uday R. Savagaonkar, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Raghunandan Makaram, Carlos V. Rozas, Amy L. Santoni, Vincent R. Scarlata, Vedvyas Shanbhogue, Ilya Alexandrovich, Ittai Anati, Wesley H. Smith, Michael Goldsmith
  • Patent number: 10409597
    Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Rebekah Leslie-Hurd, Carlos V. Rozas, Vincent R. Scarlata, Simon P. Johnson, Uday R. Savagaonkar, Barry E. Huntley, Vedvyas Shanbhogue, Ittai Anati, Francis X. Mckeen, Michael A. Goldsmith, Ilya Alexandrovich, Alex Berenzon, Wesley H. Smith, Gilbert Neiger