Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed including at least one memory; machine-readable instructions; and processor circuitry to at least one of execute or instantiate the machine-readable instructions to: obtain a register-transfer level design defining operations of electrical circuits in first and second dice of a multi-die semiconductor package, the second die to be stacked on the first die in the multi-die semiconductor package; and select placement of a cell for a physical layout for the multi-die semiconductor package based on the register-transfer level design, the cell including a via to electrically interconnect the first die to the second die.

Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

Abstract: A compound of formula (I-a): wherein the symbols are defined in the specification, and which has a strong DDR1 inhibitory activity, and can be a therapeutic agent for DDR1-related diseases, for example, a cancer, a kidney disease, a cardiovascular disease, a central nervous system disease, or fibrosis.

Abstract: Described is a resilient fluid control valve assembly. The resilient fluid control valve assembly includes a cartridge housing having an upper portion and a lower portion. The upper portion is formed to reside above a drain opening, while the lower portion is formed to reside within the drain opening. The resilient fluid control valve assembly further includes a resilient fluid control valve positioned within the cartridge housing. The resilient fluid control valve has a valve body portion and a sealing portion. When positioned within the cartridge housing, a portion of the valve body portion resides above the drain opening, and a portion of the sealing portion resides within the drain opening.

Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.

Abstract: A hybrid flushing system for water free urinals is presented with a housing having a wall portion forming a cavity for receiving a cartridge. The housing also includes a flushing fluid inlet portion for receiving a flushing fluid and a flushing fluid directing portion configured to direct the flushing fluid. A cartridge for installation into a housing is presented, including a cartridge wall, a flushing fluid receiving portion and a flushing fluid directing portion to direct flushing fluid received to any portion to clean areas of the housing, the cartridge, and connected plumbing. Steps for cleaning a hybrid flushing system are presented with an act of directing a flushing fluid into an area, where the area is one of a cartridge for a hybrid flushing system, a housing for a hybrid flushing system, and a plumbing system connected with the hybrid flushing system.

Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.

Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.

Abstract: Described is a resilient fluid control valve assembly. The resilient fluid control valve assembly includes a cartridge housing having an upper portion and a lower portion. The upper portion is formed to reside above a drain opening, while the lower portion is formed to reside within the drain opening. The resilient fluid control valve assembly further includes a resilient fluid control valve positioned within the cartridge housing. The resilient fluid control valve has a valve body portion and a sealing portion. When positioned within the cartridge housing, a portion of the valve body portion resides above the drain opening, and a portion of the sealing portion resides within the drain opening.

Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.

Abstract: A device for the disposal of human waste matter, specifically a toilet, is presented. This toilet incorporates elements designed to prevent both a loss of flushing efficiency and an extensive consumption of water, all while improving upon the basic functionalities of the toilet as such. These elements include specialized parts designed to both improve the efficacy of the “siphon jet” type toilet by precluding the possibility of aeration within certain critical components of the toilet system proper, as well as a specialized rim fed channel whose intersection of the filled jet channel always travels below the operating water level of the bowl, and a vacuum assisted flushing system, whose primary purpose is to enhance the power of the toilet's flushing action.

Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.

Abstract: A hybrid flushing system for water free urinals is presented with a housing having a wall portion forming a cavity for receiving a cartridge. The housing also includes a flushing fluid inlet portion for receiving a flushing fluid and a flushing fluid directing portion configured to direct the flushing fluid. A cartridge for installation into a housing is presented, including a cartridge wall, a flushing fluid receiving portion and a flushing fluid directing portion to direct flushing fluid received to any portion to clean areas of the housing, the cartridge, and connected plumbing. Steps for cleaning a hybrid flushing system are presented with an act of directing a flushing fluid into an area, where the area is one of a cartridge for a hybrid flushing system, a housing for a hybrid flushing system, and a plumbing system connected with the hybrid flushing system.

Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.

Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.