Patents by Inventor Michael Goldsmith
Michael Goldsmith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9766889Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.Type: GrantFiled: March 18, 2016Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Rebekah Leslie-Hurd, Carlos V. Rozas, Vincent R. Scarlata, Simon P. Johnson, Uday R. Savagaonkar, Barry E. Huntley, Vedvyas Shanbhogue, Ittai Anati, Francis X. Mckeen, Michael A. Goldsmith, Ilya Alexandrovich, Alex Berenzon, Wesley H. Smith, Gilbert Neiger
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Patent number: 9747102Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.Type: GrantFiled: December 28, 2012Date of Patent: August 29, 2017Assignee: Intel CorporationInventors: Rebekah Leslie, Carlos V. Rozas, Vincent R. Scarlata, Simon P. Johnson, Uday R. Savagaonkar, Barry E. Huntley, Vedvyas Shanbhogue, Ittai Anati, Francis X. Mckeen, Michael A. Goldsmith, Ilya Alexandrovich, Alex Berenzon, Wesley H. Smith, Gilbert G. Neiger
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Publication number: 20170198469Abstract: A non-flushing urinal system with a large sealing and flow area using a bell-shaped valve with supporting ribs on its interior surface, which utilizes low “crack pressure,” or ease of initial opening to create for high flow rate and superior sealing.Type: ApplicationFiled: January 9, 2017Publication date: July 13, 2017Inventors: Michael Wächter, Manuel Peter, Edward Michael Goldsmith
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Patent number: 9703715Abstract: Embodiments of an invention for sharing memory in a secure processing environment are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to match an offer to make a page in an enclave page cache shareable to a bid to make the page shareable. The execution unit is to execute the instruction. Execution of the instruction includes making the page shareable.Type: GrantFiled: December 28, 2013Date of Patent: July 11, 2017Assignee: Intel CorporationInventors: Michael A. Goldsmith, Simon P. Johnson, Carlos V. Rozas, Vincent R. Scarlata
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Patent number: 9698989Abstract: Embodiments of an invention for feature licensing in a secure processing environment are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to initialize a secure enclave. The execution unit is to execute the instruction. Execution of the instruction includes determining whether a requested feature is licensed for use in the secure enclave.Type: GrantFiled: July 23, 2013Date of Patent: July 4, 2017Assignee: Intel CorporationInventors: Vincent Scarlata, Carlos Rozas, Simon Johnson, Uday Savagaonkar, Ittai Anati, Francis McKeen, Michael Goldsmith
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Patent number: 9690704Abstract: Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes evicting a first page from an enclave page cache.Type: GrantFiled: April 6, 2016Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: Francis X. Mckeen, Michael A. Goldsmith, Barry E. Huntley, Simon P. Johnson, Rebekah Leslie-Hurd, Carlos V. Rozas, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, Ittai Anati, Ilya Alexandrovich, Alex Berenzon, Gilbert Neiger
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Patent number: 9674106Abstract: A method and system for establishing a helpdesk session between a subscriber device and a customer support representative (CSR) device following a request for a helpdesk session. The system issuing, on receipt of said request, a credential pair comprising subscriber credentials for a subscriber device and CSR credentials for a CSR device which is paired with the subscriber device. The subscriber credentials are transferred to the subscriber device and the CSR credentials are transferred to the CSR device. The subscriber and CSR credentials are then transferred to a core node for authentication. If the credentials are authentic the helpdesk session between the paired subscriber device and the CSR device is established.Type: GrantFiled: December 4, 2013Date of Patent: June 6, 2017Assignee: RealVNC LtdInventors: Nicolas David Reeves, Christopher Michael Goldsmith, Antony Clive Mann, Philip John Richards, Thomas Henry Lynn, Katarzyna Maria Czeczot
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Patent number: 9665724Abstract: Embodiments of an invention for logging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction having an associated enclave page cache address. The execution unit is to execute the instruction without causing a virtual machine exit, wherein execution of the instruction includes logging the instruction and the associated enclave page cache address.Type: GrantFiled: October 21, 2015Date of Patent: May 30, 2017Assignee: Intel CorporationInventors: Francis X. McKeen, Michael A. Goldsmith, Barrey E. Huntley, Simon P. Johnson, Rebekah M. Leslie-Hurd, Carlos V. Rozas, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, Gilbert Neiger
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Publication number: 20170024317Abstract: Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes evicting a first page from an enclave page cache.Type: ApplicationFiled: April 6, 2016Publication date: January 26, 2017Applicant: Intel CorporationInventors: Francis X. Mckeen, Michael A. Goldsmith, Barry E. Huntley, Simon P. Johnson, Rebekah Leslie-Hurd, Carlos V. Rozas, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, Ittai Anati, Ilya Alexandrovich, Alex Berenzon, Gilbert Neiger
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Publication number: 20160371191Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.Type: ApplicationFiled: August 29, 2016Publication date: December 22, 2016Inventors: CARLOS V. ROZAS, ILYA ALEXANDROVICH, ITTAI ANATI, ALEX BERENZON, MICHAEL A. GOLDSMITH, BARRY E. HUNTLEY, ANTON IVANOV, SIMON P. JOHNSON, REBEKAH M. LESLIE-HURD, FRANCIS X. MCKEEN, GILBERT NEIGER, RINAT RAPPOPORT, SCOTT D. RODGERS, UDAY R. SAVAGAONKAR, VINCENT R. SCARLATA, VEDVYAS SHANBHOGUE, WESLEY H. SMITH, WILLIAM C. WOOD
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Publication number: 20160364338Abstract: A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.Type: ApplicationFiled: June 12, 2015Publication date: December 15, 2016Inventors: Krystof C. Zmudzinski, Siddhartha Chhabra, Uday R. Savagaonkar, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Raghunandan Makaram, Carlos V. Rozas, Amy L. Santoni, Vincent R. Scarlata, Vedvyas Shanbhogue, Ilya Alexandrovich, Ittai Anati, Wesley H. Smith, Michael Goldsmith
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Patent number: 9519803Abstract: In accordance with some embodiments, a protected execution environment may be defined for a graphics processing unit. This framework not only protects the workloads from malware running on the graphics processing unit but also protects those workloads from malware running on the central processing unit. In addition, the trust framework may facilitate proof of secure execution by measuring the code and data structures used to execute the workload. If a part of the trusted computing base of this framework or protected execution environment is compromised, that part can be patched remotely and the patching can be proven remotely throughout attestation in some embodiments.Type: GrantFiled: November 30, 2012Date of Patent: December 13, 2016Assignee: Intel CorporationInventors: Prashant Dewan, Uday R. Savagaonkar, David M. Durham, Paul S. Schmitz, Jason Martin, Michael Goldsmith, Ravi L. Sahita, Francis X. McKeen, Carlos Rozas, Balaji Vembu, Scott Janus, Geoffrey S. Strongin, Xiaozhu Kang, Karanvir S. Grewal, Siddhartha Chhabra, Alpha T. Narendra Trivedi
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Publication number: 20160356032Abstract: A device for the disposal of human waste matter, specifically a toilet, is presented. This toilet incorporates elements designed to prevent both a loss of flushing efficiency and an extensive consumption of water, all while improving upon the basic functionalities of the toilet as such. These elements include specialized parts designed to both improve the efficacy of the “siphon jet” type toilet by precluding the possibility of aeration within certain critical components of the toilet system proper, as well as a specialized rim fed channel whose intersection of the filled jet channel always travels below the operating water level of the bowl, and a vacuum assisted flushing system, whose primary purpose is to enhance the power of the toilet's flushing action.Type: ApplicationFiled: February 2, 2016Publication date: December 8, 2016Inventors: Philip Hennessy, Edward Michael Goldsmith
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Publication number: 20160273666Abstract: Described is a duckbill valve assembly for connecting with a waterless urinal. The assembly includes a sleeve for containing a duckbill valve therein. The duckbill valve includes a trough with two substantially parallel sheets forming a sealing area. At least one of the substantially parallel sheets includes a side pleat. When the parallel sheets separate as the valve opens, the side pleat expands, increasing the opening cross-sectional area over that afforded by the parallel sheets alone.Type: ApplicationFiled: January 20, 2015Publication date: September 22, 2016Inventor: Edward Michael Goldsmith
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Patent number: 9430384Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.Type: GrantFiled: March 31, 2013Date of Patent: August 30, 2016Assignee: Intel CorporationInventors: Carlos V Rozas, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael A Goldsmith, Barry E Huntley, Anton Ivanov, Simon P Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Rinat Rappoport, Scott Dion Rodgers, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H Smith, William Colin Wood
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Publication number: 20160202976Abstract: Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.Type: ApplicationFiled: March 18, 2016Publication date: July 14, 2016Applicant: Intel CorporationInventors: Rebekah Leslie-Hurd, Carlos V. Rozas, Vincent R. Scarlata, Simon P. Johnson, Uday R. Savagaonkar, Barry E. Huntley, Vedvyas Shanbhogue, Ittai Anati, Francis X. Mckeen, Michael A. Goldsmith, Ilya Alexandrovich, Alex Berenzon, Wesley H. Smith, Gilbert Neiger
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Publication number: 20160188354Abstract: Embodiments of an invention for efficient enabling of EPTs are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to switch an extended page table pointer (EPTP) in a non-root mode. The control logic is logic to determine, in response to receiving the instruction, whether to cause a first virtual machine exit, wherein the determination is based on whether a valid entry is found in an active EPTP list. The execution hardware is to execute a virtual machine monitor, wherein the virtual machine monitor is to activate a populated EPTP list in response to determining that extended page tables are being used and to activate an unpopulated EPTP list in response to determining that extended page tables are not being used.Type: ApplicationFiled: December 24, 2014Publication date: June 30, 2016Inventors: Michael Goldsmith, Ravi Sahita
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Publication number: 20160170900Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.Type: ApplicationFiled: February 19, 2016Publication date: June 16, 2016Applicant: Intel CorporationInventors: Gur Hildesheim, Shlomo Raikin, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis Mckeen, Carlos Rozas, Michael Goldsmith, Prashant Dewan
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Patent number: 9355262Abstract: Embodiments of an invention for modifying memory permissions in a secure processing environment are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to modify access permissions for a page in a secure enclave. The execution unit is to execute the instruction. Execution of the instruction includes setting new access permissions in an enclave page cache map entry. Furthermore, the page is immediately accessible from inside the secure enclave according to the new access permissions.Type: GrantFiled: December 27, 2013Date of Patent: May 31, 2016Assignee: Intel CorporationInventors: Rebekah Leslie-Hurd, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael Goldsmith, Simon Johnson, Francis McKeen, Carlos Rozas, Uday Savagaonkar, Vincent Scarlata, Vedvyas Shanbhogue, Wesley Smith
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Patent number: 9323686Abstract: Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes evicting a first page from an enclave page cache.Type: GrantFiled: December 28, 2012Date of Patent: April 26, 2016Assignee: Intel CorporationInventors: Francis X. Mckeen, Michael A. Goldsmith, Barry E. Huntley, Simon P. Johnson, Rebekah Leslie, Carlos V. Rozas, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, Ittai Anati, Ilya Alexandrovich, Alex Berenzon, Gilbert Neiger