Patents by Inventor Michael Graf

Michael Graf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7851326
    Abstract: A method for producing deep trench structures in an STI structure of a semiconductor substrate is provided, with the following successive process steps: subsequent to a full-area filling of STI recesses introduced into a semiconductor substrate with a first filler material, a first surface of a semiconductor structure is subjected to a CMP process to level the applied filler material and produce the STI structure; the leveled STI structure thus produced is structured; using the structured, leveled STI structure as a hard mask, at least one deep trench is etched in the area of this STI structure to create the deep trench structures.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: December 14, 2010
    Assignee: TELEFUNKEN Semiconductors GmbH & Co. KG
    Inventors: Franz Dietz, Volker Dudek, Michael Graf, Thomas Hoffmann
  • Publication number: 20100312503
    Abstract: The invention relates to a method for determining the filling time for filling at least one material separator (1) provided with a fill level sensor (12) and a requirement sensor (11) in delivery systems made of at least one reservoir (4) with bulk material. In the beginning, with empty lines (3, 6) and an empty material separator (1), the bulk material is delivered out of the reservoir (4) from the time the requirement sensor (11) is triggered until the fill level sensor (12) is triggered, and said delivery time (TREF1) is measured and stored. If the requirement sensor (11) is triggered again, the delivery is carried out again until the fill level sensor (12) is triggered, and said delivery time (TREF2), which corresponds to the delivery time for filling the material separator (1), is measured and stored, whereby bulk material is present in the lines (3, 6) from the first delivery.
    Type: Application
    Filed: December 16, 2008
    Publication date: December 9, 2010
    Applicant: WITTMANN KUNSTSTOFFGERAETE GMBH
    Inventors: Erhard Fux, Michael Graf
  • Patent number: 7848070
    Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: December 7, 2010
    Assignee: Atmel Corporation
    Inventors: Stefan Schwantes, Michael Graf, Volker Dudek, Gayle W. Miller, Jr., Irwin Rathbun, Peter Grombach, Manfred Klaussner
  • Publication number: 20100200774
    Abstract: A method of forming a thin film on a substrate is described. The method comprises depositing a first material layer on a substrate using a first gas cluster ion beam (GCIB), the first material layer comprising a first atomic constituent, and growing a second material layer from at least a surface portion of the first material layer by introducing a second atomic constituent using a second GCIB, the second material layer comprising a reaction product of the first and second atomic constituents.
    Type: Application
    Filed: February 9, 2009
    Publication date: August 12, 2010
    Applicant: TEL Epion Inc.
    Inventors: Edmund Burke, John J. Hautala, Michael Graf
  • Publication number: 20100193708
    Abstract: Disclosed are methods of operation to grow, modify, deposit, or dope a layer upon a substrate using a multi-nozzle and skimmer assembly for introducing a process gas mixture, or multiple process gases mixtures, in a gas cluster ion beam (GCIB) system. Also disclosed is a method of forming a shallow trench isolation (STI) structure on a substrate, for example, an SiO2 STI structure, using a multiple nozzle system with two separate gas supplies, for example providing a silicon-containing gas and an oxygen-containing gas.
    Type: Application
    Filed: April 23, 2009
    Publication date: August 5, 2010
    Applicant: TEL EPION INC.
    Inventors: Martin D. Tabat, Matthew C. Gwinn, Robert K. Becker, Avrum Freytsis, Michael Graf
  • Publication number: 20100193701
    Abstract: Disclosed is a multi-nozzle and skimmer assembly for introducing a process gas mixture, or multiple process gases mixtures, in a gas cluster ion beam (GCIB) system, and associated methods of operation to grow, modify, deposit, or dope a layer upon a substrate. The multiple nozzle and skimmer assembly includes at least two nozzles arranged in mutual close proximity to at least partially coalesce the gas cluster beams emitted therefrom into a single gas cluster beam and/or angled to converge each beam toward a single intersecting point to form a set of intersecting gas cluster beams, and to direct the single and/or intersecting gas cluster beam into a gas skimmer.
    Type: Application
    Filed: April 23, 2009
    Publication date: August 5, 2010
    Applicant: TEL Epion Inc.
    Inventors: Martin D. Tabat, Matthew C. Gwinn, Robert K. Becker, Avrum Freytsis, Michael Graf
  • Publication number: 20100193472
    Abstract: A gas cluster ion beam (GCIB) processing system using multiple nozzles for forming and emitting at least one GCIB and methods of operating thereof are described. The GCIB processing system may be configured to treat a substrate, including, but not limited to, doping, growing, depositing, etching, smoothing, amorphizing, or modifying a layer thereupon. Furthermore, the GCIB processing system may be operated to produce a first GCIB and a second GCIB, and to irradiate a substrate simultaneously and/or sequentially with the first GCIB and second GCIB.
    Type: Application
    Filed: March 26, 2010
    Publication date: August 5, 2010
    Applicant: TEL EPION INC.
    Inventors: Martin D. Tabat, Matthew C. Gwinn, Robert K. Becker, Avrum Freytsis, Michael Graf
  • Publication number: 20100013256
    Abstract: A console is provided, in particular a central console for a vehicle, having a rail pair for the essentially horizontally displaceable accommodation of inserts of the console between the rails of the rail pair in guides of the rails, as well as a storage space between the inserts and the floor of the vehicle. For such a console, it is provided that the rails are implemented as freestanding brackets, the brackets at least being mounted in the floor of the vehicle, an essentially horizontally situated section of the particular bracket, which is distal from the floor, having at least one guide. Such a console offers high flexibility in regard to the storage space usable in this area with structurally simple design and may be advantageously used both with and also without the inserts in this aspect.
    Type: Application
    Filed: June 22, 2007
    Publication date: January 21, 2010
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, INC.
    Inventors: Stefan Arndt, Matthias Blanck, Andreas Dorhöfer, Uwe Fett, Michael Graf, Michael Renkel
  • Publication number: 20090317564
    Abstract: A method of forming a thin film on a substrate is described. The method comprises providing a substrate in a reduced-pressure environment, and generating a gas cluster ion beam (GCIB) in the reduced-pressure environment from a pressurized gas mixture. A beam acceleration potential and a beam dose are set to achieve a thickness of the thin film ranging up to about 300 angstroms and to achieve a surface roughness of an upper surface of the thin film that is less than about 20 angstroms. The GCIB is accelerated according to the beam acceleration potential, and the accelerated GCIB is irradiated onto at least a portion of the substrate according to the beam dose. By doing so, the thin film is grown on the at least a portion of the substrate to achieve the thickness and the surface roughness.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 24, 2009
    Applicant: TEL EPION INC.
    Inventors: John J. Hautala, Michael Graf, Yan Shao, Brian S. Freer
  • Publication number: 20090273883
    Abstract: A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.
    Type: Application
    Filed: July 13, 2009
    Publication date: November 5, 2009
    Inventors: Stefan Schwantes, Volker Dudek, Michael Graf, Alan Renninger, James Shen
  • Publication number: 20090266997
    Abstract: An ion implanter system including an ion source for use in creating a stream or beam of ions. The ion source has an ion source chamber housing that at least partially bounds an ionization region for creating a high density concentration of ions within the chamber housing. An ion extraction aperture of desired characteristics covers an ionization region of the chamber. In one embodiment, a movable ion extraction aperture plate is moved with respect to the housing for modifying an ion beam profile. One embodiment includes an aperture plate having at least elongated apertures and is moved between at least first and second positions that define different ion beam profiles. A drive or actuator coupled to the aperture plate moves the aperture plate between the first and second positions. An alternate embodiment has two moving plate portions that bound an adjustable aperture.
    Type: Application
    Filed: April 14, 2009
    Publication date: October 29, 2009
    Applicant: Axcelis Technologies, Inc.
    Inventors: Daniel Tieger, William DiVergilio, Edward Eisner, Michael Graf
  • Publication number: 20090258472
    Abstract: Method for manufacturing a semiconductor array, in which a conductive substrate (100), a component region (400), and an insulation layer (200), isolating the component region (400) from the conductive substrate (100), are formed, a trench (700) is etched in the component region (400) as far as the insulation layer (200), then the trench (700) is etched further as far as the conductive substrate (100), the walls (701) of the trench (700) are formed with an insulation material (710), and an electrical conductor (750, 755, 760) is introduced into the trench (700) and connected conductively to the conductive substrate (100), wherein before the trench (700) is etched, a layer sequence comprising a first oxide layer (510), a polysilicon layer (520) on top of the first oxide layer (510), and a second oxide layer (530) on top of the polysilicon layer (520) is applied to the component region (400).
    Type: Application
    Filed: September 28, 2006
    Publication date: October 15, 2009
    Applicant: ATMEL Germany GmbH
    Inventors: Tobias Florian, Michael Graf, Stefan Schwantes
  • Publication number: 20090212586
    Abstract: A mounting of a container in a rail pair is provided, which is disposed in a passenger compartment of a motor vehicle, and the rails of the rail pair have substantially horizontally extending guide grooves on the mutually facing sides and a projection is mounted in the container on its side facing the respective rail, and the respective guide groove has a cross section which expands from the groove base and the respective projection has a corresponding cross section which is expanded toward the container.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 27, 2009
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, INC.
    Inventors: Matthias BLANCK, Michael GRAF, Andreas DORHOFER
  • Patent number: 7560334
    Abstract: A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: July 14, 2009
    Assignee: Atmel Corporation
    Inventors: Stefan Schwantes, Volker Dudek, Michael Graf, Alan Renninger, James Shen
  • Patent number: 7521756
    Abstract: A lateral DMOS transistor is disclosed that includes a first region of a first conductivity type, which is surrounded on the sides by a second region of a second conductivity type, whereby a boundary line between both regions has opposite straight sections and curved sections linking the straight sections, and with a first dielectric structure, which serves as a field region and is embedded in the first region and surrounds a subregion of the first region. Whereby the first distance between the first dielectric structure and the boundary line is greater along the straight sections than along the curved sections.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: April 21, 2009
    Assignee: Atmel Germany GmbH
    Inventors: Franz Dietz, Michael Graf, Stefan Schwantes
  • Patent number: 7504692
    Abstract: High-voltage field-effect transistor is provided that includes a drain terminal, a source terminal, a body terminal, and a gate terminal. A gate oxide and a gate electrode, adjacent to the gate oxide, is connected to the gate terminal. A drain semiconductor region of a first conductivity type is connected to the drain terminal. A source semiconductor region of a first conductivity type is connected to the source terminal. A body terminal semiconductor region of a second conductivity type is connected to the body terminal. A body semiconductor region of the second conductivity type, is partially adjacent to the gate oxide to form a channel and is adjacent to the body terminal semiconductor region. A drift semiconductor region of the first conductivity type is adjacent to the drain semiconductor region and the body semiconductor region, wherein in the drift semiconductor region, a potential barrier is formed in a region distanced from the body semiconductor region.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: March 17, 2009
    Assignee: Atmel Germany GmbH
    Inventors: Volker Dudek, Michael Graf, Stefan Schwantes
  • Publication number: 20080290426
    Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.
    Type: Application
    Filed: August 4, 2008
    Publication date: November 27, 2008
    Applicant: Atmel Corporation
    Inventors: Gayle W. Miller, Irwin D. Rathbun, Stefan Schwantes, Michael Graf, Volker Dudek
  • Publication number: 20080278874
    Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.
    Type: Application
    Filed: July 21, 2008
    Publication date: November 13, 2008
    Inventors: Stefan Schwantes, Michael Graf, Volker Dudek, Gayle W. Miller, JR., Irwin Rathbun, Peter Grombach, Manfred Klaussner
  • Publication number: 20080256905
    Abstract: In one example embodiment, a system for opening a valve bag includes a bag separator assembly and a valve opening assembly. The bag separator assembly is rotatable about a rotation axis and is configured to move along a taxis toward a plurality of valve bags to obtain a valve bag. The bag separator assembly also is configured to move along the y-axis in an opposing direction to separate the valve bag from the plurality of valve bags. The rotation axis and y-axis are perpendicular to one another. The valve opening assembly is configured to open a valve end of the valve bag. The valve opening assembly also is configured to move along an x-axis to be inserted into and removed from the valve end of a valve bag being held by the bag separator assembly. The bag separator assembly avoids contact with the valve opening assembly by rotating about the rotation axis before moving along the y-axis toward the plurality of valve bags.
    Type: Application
    Filed: April 18, 2008
    Publication date: October 23, 2008
    Inventor: MICHAEL GRAF
  • Patent number: 7407851
    Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: August 5, 2008
    Inventors: Gayle W. Miller, Irwin D. Rathbun, Stefan Schwantes, Michael Graf, Volker Dudek