Abstract: A lateral DMOS transistor is disclosed that includes a first region of a first conductivity type, which is surrounded on the sides by a second region of a second conductivity type, whereby a boundary line between both regions has opposite straight sections and curved sections linking the straight sections, and with a first dielectric structure, which serves as a field region and is embedded in the first region and surrounds a subregion of the first region. Whereby the first distance between the first dielectric structure and the boundary line is greater along the straight sections than along the curved sections.

Abstract: High-voltage field-effect transistor is provided that includes a drain terminal, a source terminal, a body terminal, and a gate terminal. A gate oxide and a gate electrode, adjacent to the gate oxide, is connected to the gate terminal. A drain semiconductor region of a first conductivity type is connected to the drain terminal. A source semiconductor region of a first conductivity type is connected to the source terminal. A body terminal semiconductor region of a second conductivity type is connected to the body terminal. A body semiconductor region of the second conductivity type, is partially adjacent to the gate oxide to form a channel and is adjacent to the body terminal semiconductor region. A drift semiconductor region of the first conductivity type is adjacent to the drain semiconductor region and the body semiconductor region, wherein in the drift semiconductor region, a potential barrier is formed in a region distanced from the body semiconductor region.

Abstract: A hybrid ion source, comprising a source body configured to create plasma therein, from a first material, wherein the first material comprises one of monatomic gases, small molecule gases, large molecule gases, reactive gases, and solids, a low power plasma generation component operably associated with the source body, a high power plasma generation component operably associated with the source body and an extraction aperture configured to extract ions of the ion plasma from the source body.

Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.

Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.

Abstract: One embodiment of the invention relates to an apparatus for profiling an ion beam. The apparatus includes a current measuring device having a measurement region, wherein a cross-sectional area of the ion beam enters the measurement region. The apparatus also includes a controller configured to periodically take beam current measurements of the ion beam and to determine a two dimensional profile of the ion beam by relating the beam current measurements to sub-regions within the current measuring device. Other apparatus and methods are also disclosed.

Abstract: In one example embodiment, a system for opening a valve bag includes a bag separator assembly and a valve opening assembly. The bag separator assembly is rotatable about a rotation axis and is configured to move along a taxis toward a plurality of valve bags to obtain a valve bag. The bag separator assembly also is configured to move along the y-axis in an opposing direction to separate the valve bag from the plurality of valve bags. The rotation axis and y-axis are perpendicular to one another. The valve opening assembly is configured to open a valve end of the valve bag. The valve opening assembly also is configured to move along an x-axis to be inserted into and removed from the valve end of a valve bag being held by the bag separator assembly. The bag separator assembly avoids contact with the valve opening assembly by rotating about the rotation axis before moving along the y-axis toward the plurality of valve bags.

Abstract: An image monitor system monitors characteristics of an ion beam employed in ion implantation. The monitored characteristics can include particle count, particle information, beam current intensity, beam shape, and the like. The system includes one or more image sensors that capture frames or images along a beam path of an ion beam. An image analyzer analyzes the captured frames to obtain measured characteristics. A controller determines adjustments or corrections according to the measured characteristics and desired beam characteristics.

Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.

Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.

Abstract: A workpiece or semiconductor wafer is tilted as a ribbon beam is swept up and/or down the workpiece. In so doing, the implant angle or the angle of the ion beam relative to the workpiece remains substantially constant across the wafer. This allows devices to be formed substantially consistently on the wafer. Resolving plates move with the beam as the beam is scanned up and/or down. This allows desired ions to impinge on the wafer, but blocks undesirable contaminants.

Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

Abstract: An ion implantation cluster tool for implanting ions into a workpiece is provided, wherein a plurality of beamline assemblies having a respective plurality of ion beamlines associated therewith are positioned about a common process chamber. Each of the plurality of ion beamline assemblies are selectively isolated from the common process chamber, and the plurality of beamline intersect at a processing region of the process chamber. A scanning apparatus positioned within the common process chamber is operable to selectively translate a workpiece holder in one or more directions through each of the plurality of ion beamlines within the processing region, and a common dosimetry apparatus within the common process chamber is operable to measure one or more properties of each of the plurality of ion beamlines. A load lock chamber is operably coupled to the common process chamber for exchange of workpieces between the common process chamber and an external environment.

Abstract: An ion implanter includes an ion source for generating an ion beam moving along a beam line and a vacuum or implantation chamber wherein a workpiece, such as a silicon wafer is positioned to intersect the ion beam for ion implantation of a surface of the workpiece by the ion beam. A liner has an interior facing surface that bounds at least a portion of the evacuated interior region and that comprises grooves spaced across the surface of the liner to capture contaminants generated within the interior region during operation of the ion implanter.

Abstract: Beam current is adjusted during ion implantation by adjusting one or more parameters of an ion source. The ion beam is generated or provided by a non-arc discharge based ion source, such as an electron gun driven ion source or an RF driven ion source. A beam current adjustment amount is determined. Then, one or more parameters of the ion source are adjusted according to the determined beam current adjustment amount. The beam current is provided having a modulated beam current.

Abstract: An ion beam is rapidly switched off during ion implantation on detecting a beam instability. The ion beam is generated or provided by a non-arc discharge based ion source, such as an electron gun ion source or an RF ion source. The ion beam is scanned across a workpiece from a starting location toward an ending location. During the scanning, one or more beam characteristics are monitored, such as beam current, beam flux, shape, and the like. An instability is detected when one or more of the beam characteristics deviate from acceptable values or levels. The ion beam is rapidly turned off on the detected instability.

Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

Abstract: An image monitor system monitors characteristics of an ion beam employed in ion implantation. The monitored characteristics can include particle count, particle information, beam current intensity, beam shape, and the like. The system includes one or more image sensors that capture frames or images along a beam path of an ion beam. An image analyzer analyzes the captured frames to obtain measured characteristics. A controller determines adjustments or corrections according to the measured characteristics and desired beam characteristics.

Abstract: The present invention is directed to a method and apparatus for providing a uniform ion implantation in a single-workpiece two-dimensional mechanical scanning ion implantation system, wherein the transient temperature operating parameter is controlled based on mechanical rotation of the workpiece by a predetermined amount between two or more scans of the workpiece through a fixed ion beam. Rotating the workpiece between scans through the fixed ion beam allows for the transient temperature to decay sufficiently for more uniform ion implantation processes to proceed.