Abstract: A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.

Abstract: A battery sensor has a current meter, an analytical unit, and a microprocessor. During an idle phase, in which the electrical main user, provided with a battery, is switched off, the following steps are carried out. The microprocessor is switched off. At given intervals the measured signal from the current meter is recorded for a given first duration by the analytical unit and allocated first current values which are monitored in the analytical unit for exceeding a first current threshold or dropping below a second current threshold. On exceeding or dropping below the current thresholds, the microprocessor is switched on and, for a given second duration, the measured signal from the current meter is recorded by the analytical unit and allocated second current values which are then analysed in the microprocessor. Procedures for obtaining the electrical charge of the battery by the microprocessor are initiated when a given condition is met, which is dependent on the second current values.

Abstract: Vertically insulated active semiconductor regions having different thicknesses in an SOI wafer, which has an insulating layer, is produced. On the wafer, first active semiconductor regions having a first thickness are arranged in a layer of active semiconductor material. The second active semiconductor regions having a relatively smaller thickness are produced by epitaxial growth proceeding from at least one seed opening in a trench structure. The second semiconductor regions are substantially completely dielectrically insulated, laterally and vertically, from the first semiconductor regions by oxide layers. The width of the seed opening can be defined by lithography.

Abstract: A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

Abstract: A device monitors the operating parameters of a battery, in particular a starter battery for an automobile. The operating parameters include at least the battery voltage and the device is supplied from the battery voltage. For power-saving and yet precise determination of operating parameters for the period of time which is particularly significant in practice after a drop in the battery voltage, the device comprises a battery parameter detection device which determines the operating parameters of the battery in an awake state, stores these in digital form and/or supplies them to a digital interface output. The detection device is inactive in a sleep state and has a reduced consumption of electricity. A cut-off detection device compares the battery voltage with the predetermined cut-off voltage during the sleep state and awakens the detection device from the sleep state if the battery voltage falls below the predetermined cut-off voltage.

Abstract: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal-semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.

Abstract: An integrated circuit is disclosed that includes a component region with at least one NDMOS transistor and at least one PDMOS transistor and a substrate, which is isolated from the component region by a dielectric, whereby the component region, dielectric, and substrate form a first substrate capacitance standardized to a unit area in a first region of the PDMOS transistor and a second substrate capacitance standardized to said unit area in a second region of the NDMOS transistor, and whereby the first substrate capacitance standardized to said unit area is reduced in comparison to the second substrate capacitance standardized to said unit area.

Abstract: A semiconductor element such as a DMOS-transistor is fabricated in a semiconductor substrate. Wells of opposite conductivity are formed by implanting and then thermally diffusing respective well dopants into preferably spaced-apart areas in the substrate. At least one trench and active regions are formed in the substrate. The trench may be a shallow drift zone trench of a DMOS-transistor, and/or a deep isolation trench. The thermal diffusion of the well dopants includes at least one first diffusion step during a first high temperature drive before forming the trench, and at least one second diffusion step during a second high temperature drive after forming the trench. Dividing the thermal diffusion steps before and after the trench formation achieves an advantageous balance between reducing or avoiding lateral overlapping diffusion of neighboring wells and reducing or avoiding thermally induced defects along the trench boundaries.

Abstract: A method for optimizing an ion implantation, wherein a substrate is scanned in two dimensions through an ion beam. The method provides a process recipe comprising one or more of a current of an ion beam, a dosage of ions, and a number of substrate passes through the beam in a slow scan direction. The beam is profiled based on the process recipe, and a size of the beam is determined. One of a plurality of differing scan speeds in a fast scan direction is selected, based on a desired uniformity of the implantation and the process recipe. The process recipe is controlled, based on one or more of the desired uniformity, a throughput time for the substrate, a desired minimum ion beam current, and one or more substrate conditions. One of a plurality of speeds in a slow scan direction is selected, based on the dosage of the implantation.

Abstract: An ESD protection circuit includes semiconductor structures as basic elements whose electrical conductivity changes in a breakdown or avalanche manner in the presence of an applied voltage which exceeds a threshold value. The ESD protection circuit has a matrix of basic elements in which a desired current capacity can be set by specifying a number of basic elements in each row, and a desired voltage capacity can be set by specifying a number of rows.

Abstract: To form a semiconductor component having active regions separated from one another by trenches as isolation structures, a method involves forming a shallow trench in a semiconductor body, thereafter forming a deep trench within the shallow trench in the semiconductor body, and thereafter completely driving dopant atoms into the semiconductor body to form a well region doped with the dopant. The dopant may be previously introduced by implantation into a surface layer, and then the dopant is finally completely driven into the well region by thermally supported diffusion after forming the deep trench. The shallow and deep trenches together form a compound trench with stepped side walls. Two oppositely doped wells may be formed on opposite sides of the compound trench, which thus isolates the two wells from one another. Active regions may be formed in the two wells.

Abstract: A DMOS-transistor has a trench bordered by a drift region including two doped wall regions and a doped floor region extending along the walls and the floor of the trench. The laterally extending floor region has a dopant concentration gradient in the lateral direction. For example, the floor region includes at least two differently-doped floor portions successively in the lateral direction. This dopant gradient in the floor region is formed by carrying out at least one dopant implantation from above through the trench using at least one mask to expose a first area while covering a second area of the floor region.

Abstract: A method for optimizing an ion implantation, wherein a substrate is scanned in two dimensions through an ion beam. The method provides a process recipe comprising one or more of a current of an ion beam, a dosage of ions, and a number of substrate passes through the beam in a slow scan direction. The beam is profiled based on the process recipe, and a size of the beam is determined. One of a plurality of differing scan speeds in a fast scan direction is selected, based on a desired uniformity of the implantation and the process recipe. The process recipe is controlled, based on one or more of the desired uniformity, a throughput time for the substrate, a desired minimum ion beam current, and one or more substrate conditions. One of a plurality of speeds in a slow scan direction is selected, based on the dosage of the implantation.

Abstract: The present invention is directed to implanting ions in a workpiece in a serial implantation process in a manner that produces one or more scan patterns on the workpiece that resemble the size, shape and/or other dimensional aspects of the workpiece. Further, the scan patterns are interleaved with one another and can continue to be produced until the entirety of the workpiece is uniformly implanted with ions.

Abstract: A monolithically integratable semiconductor structure serves for over-voltage protection in an integrated circuit or as a normal diode. The structure includes an insulating layer between a substrate and a semiconductor layer of first conductivity type, and several layers formed in the semiconductor layer. First and second layers of second conductivity type are spaced apart from one another. A third layer of first conductivity type contacts the second layer. A fourth layer of first conductivity type directly contacts and surrounds the second and third layers. A fifth layer of first conductivity type and higher dopant concentration than the semiconductor layer is disposed under the first layer. The first layer surrounds the second, third and fourth layers essentially in a ring-shape. A first electrode contacts the first layer. A second electrode contacts the second and third layers.

Abstract: An SOI wafer including an active semiconductor material layer on an insulating layer is processed to form thereon first and second active semiconductor regions that respectively have different thicknesses and that are vertically and laterally insulated. In the process, a trench is etched into the SOI wafer, seed openings are formed in the bottom of the trench to reach the underlying active material layer, the trench is filled with epitaxially grown semiconductor material progressing from the seed openings, some of the epitaxially grown material is removed to form the second active regions, and oxide layers are provided so that the second active regions are laterally and vertically insulated from the first active regions formed by remaining portions of the active semiconductor material layer.

Abstract: Ion implantation scanning systems and methods are presented for providing ions from an ion beam to a treatment surface of a workpiece, wherein a beam is electrically or magnetically scanned in a single direction or plane and an implanted workpiece is rotated about an axis that is at a non-zero angle relative to the beam scan plane, where the workpiece rotation and the beam scanning are synchronized to provide the beam to the workpiece treatment surface at a generally constant angle of incidence.

Abstract: A device for measuring a battery voltage is a self-calibrating device. The battery voltage is connected to a voltage divider formed of series-connected resistors, or components that are subject to a voltage drop. For the purposes of calibration the voltage divider is separated from the battery voltage and a reference current or reference voltage source is connected to the voltage divider in its place. The voltages dropping across the voltage divider are measured and an actual resistance ratio of the resistors of the voltage divider is calculated, based on the measured voltages. The voltage divider is then re-connected to the battery voltage that is to be measured and a battery voltage is determined with the aid of the voltage divider, taking into account the calculated resistance ratio.

Abstract: The present invention is directed to modulating ion beam current in an ion implantation system to mitigate non-uniform ion implantations, for example. Multiple arrangements are revealed for modulating the intensity of the ion beam. For example, the volume or number of ions within the beam can be altered by biasing one or more different elements downstream of the ion source. Similarly, the dosage of ions within the ion beam can also be manipulated by controlling elements more closely associated with the ion source. In this manner, the implantation process can be regulated so that the wafer can be implanted with a more uniform coating of ions.