Patents by Inventor Michael J. Seddon

Michael J. Seddon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of reducing wafer thickness
    Patent number: 10777509
    Abstract: A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: September 15, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • BACKMETAL REMOVAL METHODS
    Publication number: 20200286736
    Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 10, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
  • Semiconductor substrate production systems and related methods
    Patent number: 10770351
    Abstract: Implementations of a method of separating a wafer from a boule including semiconductor material may include: creating a damage layer in a boule comprising semiconductor material. The boule may have a first end and a second end. The method may include cooling the first end of the boule and heating the second end of the boule. A thermal gradient may be formed between the cooled first end and the heated second end. The thermal gradient may assist a silicon carbide wafer to separate from the boule at the damage layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 8, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • DIE SIDEWALL COATINGS AND RELATED METHODS
    Publication number: 20200279747
    Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 3, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. CARNEY, Yusheng LIN, Michael J. SEDDON, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
  • WAFER THINNING SYSTEMS AND RELATED METHODS
    Publication number: 20200273738
    Abstract: Implementations of systems for thinning a semiconductor substrate may include: a substrate chuck configured to receive a semiconductor substrate for thinning, a spindle, a grinding wheel coupled to the spindle, and a water medium configured to be in contact with the semiconductor substrate during thinning. An ultrasonic energy source may be directly coupled to the substrate chuck, the spindle, the grinding wheel, the water medium, or any combination thereof.
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Backside wafer alignment methods
    Patent number: 10755956
    Abstract: Implementations of a method for wafer alignment may include: providing a wafer having a first side and a second side and forming a seed layer on a second side of the wafer. The method may include applying a glop to the seed layer at two or more predetermined points and plating a metal layer over the seed layer and around the glop. The method may include removing the glop to expose the seed layer and etching the seed layer to expose a plurality of alignment features on the second side of the wafer.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: August 25, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Takashi Noma
  • SEMICONDUCTOR SUBSTRATE DIE SAWING SINGULATION SYSTEMS AND METHODS
    Publication number: 20200266106
    Abstract: Implementations of methods of cutting a semiconductor substrate may include aligning a first saw blade substantially perpendicularly with a crystal plane of a non-cubic crystalline lattice of a semiconductor substrate coupled with a backmetal layer and cutting through at least a majority of the semiconductor substrate at an angle substantially perpendicular with the crystal plane of the non-cubic crystalline lattice of the semiconductor substrate. The method may also include aligning a second saw blade substantially perpendicularly with the semiconductor substrate and cutting entirely through the semiconductor substrate and the backmetal layer using the second saw blade.
    Type: Application
    Filed: May 6, 2020
    Publication date: August 20, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • SEMICONDUCTOR PACKAGE ELECTRICAL CONTACTS AND RELATED METHODS
    Publication number: 20200258752
    Abstract: Implementations of a semiconductor package may include a semiconductor die including a first side and a second side, the first side of the semiconductor die including one or more electrical contacts; and an organic material covering at least the first side of the semiconductor die. Implementations may include where the one or more electrical contacts extend through one or more openings in the organic material; a metal-containing layer coupled to the one or more electrical contacts; and one or more slugs coupled to one of a first side of the semiconductor die, a second side of the semiconductor die, or both the first side of the semiconductor die and the second side of the semiconductor die.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Michael J. Seddon, Francis J. Carney, Takashi Noma, Eiji Kurose
  • SILICON-ON-INSULATOR DIE SUPPORT STRUCTURES AND RELATED METHODS
    Publication number: 20200258751
    Abstract: Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Francis J. CARNEY, Eiji KUROSE, Chee Hiong CHEW, Soon Wei WANG
  • DIE SUPPORT STRUCTURES AND RELATED METHODS
    Publication number: 20200258750
    Abstract: Implementations of a semiconductor device may include a semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface, and a permanent die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The thickness may be between 0.1 microns and 125 microns. The warpage of the semiconductor die may be less than 200 microns.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. CARNEY, Michael J. SEDDON, Eiji KUROSE, Chee Hiong CHEW, Soon Wei WANG, Yusheng LIN
  • Stacked semiconductor device structure and method
    Patent number: 10741484
    Abstract: A method of forming stacked semiconductor device structure includes providing a first semiconductor device and a second semiconductor device. The first semiconductor device includes a recessed region bounded by sidewall portions and a conductive layer disposed adjoining at least portions of the recessed region. The method includes electrically connecting the second semiconductor device to the conductive layer within the recessed region such that at least a portion of the second semiconductor device is disposed within the recessed region.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: August 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • SOI substrate and related methods
    Patent number: 10741487
    Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Mark Griswold
  • PARTIAL BACKSIDE METAL REMOVAL SINGULATION SYSTEM AND RELATED METHODS
    Publication number: 20200243389
    Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, forming a groove only partially through a thickness of the backside metal layer, and singulating the plurality of die included in the substrate through removing backmetal material in the die street and removing substrate material in the die street. The groove may be located in a die street of the substrate.
    Type: Application
    Filed: July 8, 2019
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • SUBSTRATE ALIGNMENT SYSTEMS AND RELATED METHODS
    Publication number: 20200243366
    Abstract: Implementations of a method of making a plurality of alignment marks on a wafer may include: providing a wafer including an alignment feature on a first side of the wafer. The method may include aligning the wafer using a camera focused on the first side of the wafer. The wafer may be aligned using the alignment feature on the first side of the die. The wafer may also include creating a plurality of alignment marks on a second side of the wafer through lasering, sawing, or scribing.
    Type: Application
    Filed: July 9, 2019
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Takashi NOMA
  • BACKSIDE METAL REMOVAL DIE SINGULATION SYSTEMS AND RELATED METHODS
    Publication number: 20200243388
    Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include forming a groove through a backside metal layer through laser ablating a backside metal layer at a die street of a substrate and singulating a plurality of die included in the substrate through removing substrate material of the substrate in the die street.
    Type: Application
    Filed: July 8, 2019
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • METHODS OF ALIGNING A SEMICONDUCTOR WAFER FOR SINGULATION
    Publication number: 20200243392
    Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.
    Type: Application
    Filed: July 9, 2019
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Takashi NOMA
  • BACKSIDE METAL PATTERNING DIE SINGULATION SYSTEM AND RELATED METHODS
    Publication number: 20200243391
    Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.
    Type: Application
    Filed: July 9, 2019
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • BACKSIDE METAL PHOTOLITHOGRAPHIC PATTERNING DIE SINGULATION SYSTEMS AND RELATED METHODS
    Publication number: 20200243329
    Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and forming a groove at the pattern of the photoresist layer only partially through a thickness of the backside metal layer. The groove may be located in the die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the photoresist layer, and singulating the plurality of die included in the substrate by removing substrate material in the die street.
    Type: Application
    Filed: July 9, 2019
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Takashi NOMA, Michael J. SEDDON
  • SEMICONDUCTOR WAFER THINNING SYSTEMS AND RELATED METHODS
    Publication number: 20200243337
    Abstract: Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.
    Type: Application
    Filed: April 17, 2020
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Thomas NEYER
  • BACKSIDE METAL PATTERNING DIE SINGULATION SYSTEMS AND RELATED METHODS
    Publication number: 20200243381
    Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a seed layer on a second side of a substrate opposite the first side of the substrate, using a shadow mask, applying a mask layer over the seed layer, forming a backside metal layer over the seed layer, removing the mask layer, and singulating the plurality of die included in the substrate through removing substrate material in the die street and through removing seed layer material in the die street.
    Type: Application
    Filed: July 9, 2019
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON