Patents by Inventor Michael J. Seddon

Michael J. Seddon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BACKSIDE METAL PATTERNING DIE SINGULATION SYSTEMS AND RELATED METHODS
    Publication number: 20200243390
    Abstract: Implementations of methods of singulating a plurality of die comprised in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a polymer layer over the backside metal layer and forming a groove entirely through the polymer layer and partially through a thickness of the backside metal layer. The groove may be located in a die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the polymer layer, singulating the plurality of die in the substrate by removing substrate material in the die street.
    Type: Application
    Filed: July 9, 2019
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • BACKSIDE WAFER ALIGNMENT METHODS
    Publication number: 20200243367
    Abstract: Implementations of a method for wafer alignment may include: providing a wafer having a first side and a second side and forming a seed layer on a second side of the wafer. The method may include applying a glop to the seed layer at two or more predetermined points and plating a metal layer over the seed layer and around the glop. The method may include removing the glop to expose the seed layer and etching the seed layer to expose a plurality of alignment features on the second side of the wafer.
    Type: Application
    Filed: July 9, 2019
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. SEDDON, Takashi NOMA
  • BACKSIDE METAL FORMATION METHODS AND SYSTEMS
    Publication number: 20200232086
    Abstract: Implementations of methods of forming a metal layer on a semiconductor wafer may include: placing a semiconductor wafer into an evaporator dome and adding a material to a crucible located a predetermined distance from the semiconductor wafer. The semiconductor wafer may include an average thickness of less than 39 microns. The method may also include heating the material in the crucible to a vapor and depositing the material on a second side of the semiconductor wafer.
    Type: Application
    Filed: January 23, 2019
    Publication date: July 23, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • PLASMA DIE SINGULATION SYSTEMS AND RELATED METHODS
    Publication number: 20200219769
    Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include exposing a substrate material of a substrate in a die street through removing a metal layer in the die street coupled to the substrate, wherein only a portion of the substrate material in the die street is removed, and singulating a plurality of die included in the substrate through plasma etching the exposed substrate material of the substrate in the die street.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 9, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • JET ABLATION DIE SINGULATION SYSTEMS AND RELATED METHODS
    Publication number: 20200203226
    Abstract: Implementations of a method singulating a plurality of semiconductor die. Implementations may include: forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate where the semiconductor substrate includes a plurality of semiconductor die. The method may include etching substantially through a thickness of the semiconductor substrate at the pattern in the back metal layer and jet ablating a layer of passivation material coupled to a second side of the semiconductor substrate to singulate the plurality of semiconductor die.
    Type: Application
    Filed: March 3, 2020
    Publication date: June 25, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Wafer thinning systems and related methods
    Patent number: 10685863
    Abstract: Implementations of systems for thinning a semiconductor substrate may include: a substrate chuck configured to receive a semiconductor substrate for thinning, a spindle, a grinding wheel coupled to the spindle, and a water medium configured to be in contact with the semiconductor substrate during thinning. An ultrasonic energy source may be directly coupled to the substrate chuck, the spindle, the grinding wheel, the water medium, or any combination thereof.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 16, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Semicoductor wafer and method of backside probe testing through opening in film frame
    Patent number: 10685891
    Abstract: A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center region of the tape portion of the film frame. The film frame may have conductive traces formed on or through the tape portion. A thin semiconductor wafer includes a conductive layer formed over a surface of the semiconductor wafer. The semiconductor wafer is mounted over the opening in the tape portion of the film frame. A wafer probe chuck includes a lower surface and raised surface. The film frame is mounted to the wafer probe chuck with the raised surface extending through the opening in the tape portion to contact the conductive layer of the semiconductor wafer. The semiconductor wafer is probe tested through the opening in the tape portion of the film frame.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 16, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Heng Chen Lee
  • THINNED SEMICONDUCTOR WAFER
    Publication number: 20200185334
    Abstract: A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • CURRENT SENSOR PACKAGES
    Publication number: 20200185600
    Abstract: A semiconductor package includes a semiconductor die. A through hole in the semiconductor package and semiconductor die extends from one side of the semiconductor package and die to an opposite side of the semiconductor package and die. The through hole is configured to receive a current-carrying conductor there through. At least one current sensor is formed in, or on, the semiconductor die and configured to sense current flow in the current-carrying conductor received in the through hole.
    Type: Application
    Filed: February 19, 2020
    Publication date: June 11, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. HALL, Michael J. SEDDON, Yenting WEN
  • Semiconductor substrate die sawing singulation systems and methods
    Patent number: 10679898
    Abstract: Implementations of methods of cutting a semiconductor substrate may include aligning a first saw blade substantially perpendicularly with a crystal plane of a non-cubic crystalline lattice of a semiconductor substrate coupled with a backmetal layer and cutting through at least a majority of the semiconductor substrate at an angle substantially perpendicular with the crystal plane of the non-cubic crystalline lattice of the semiconductor substrate. The method may also include aligning a second saw blade substantially perpendicularly with the semiconductor substrate and cutting entirely through the semiconductor substrate and the backmetal layer using the second saw blade.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: June 9, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • SEMICONDUCTOR SUBSTRATE CRACK MITIGATION SYSTEMS AND RELATED METHODS
    Publication number: 20200176336
    Abstract: Implementations of a method for healing a crack in a semiconductor substrate may include identifying a crack in a semiconductor substrate and heating an area of the semiconductor substrate including the crack until the crack is healed.
    Type: Application
    Filed: February 7, 2020
    Publication date: June 4, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Semiconductor wafer thinning systems and related methods
    Patent number: 10665458
    Abstract: Semiconductor substrate thinning systems and methods. Implementations of a method of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface and inducing damage into a portion of the semiconductor substrate adjacent to the second surface forming a damage layer. The method may also include backgrinding the second surface of the semiconductor substrate.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: May 26, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Thomas Neyer
  • ABSOLUTE AND DIFFERENTIAL PRESSURE SENSORS AND RELATED METHODS
    Publication number: 20200123002
    Abstract: Implementations of absolute pressure sensor devices may include a microelectromechanical system (MEMS) absolute pressure sensor coupled over a controller die. The MEMS absolute pressure sensor may be mechanically coupled to the controller die and may also be configured to electrically couple with the controller die. A perimeter of the controller die may be one of the same size and larger than a perimeter of the MEMS absolute pressure sensor. The controller die may be configured to electrically couple with a module through an electrical connector.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Thinned semiconductor wafer
    Patent number: 10615127
    Abstract: A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: April 7, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Jet ablation die singulation systems and related methods
    Patent number: 10607889
    Abstract: Implementations of a method singulating a plurality of semiconductor die. Implementations may include: forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate where the semiconductor substrate includes a plurality of semiconductor die. The method may include etching substantially through a thickness of the semiconductor substrate at the pattern in the back metal layer and jet ablating a layer of passivation material coupled to a second side of the semiconductor substrate to singulate the plurality of semiconductor die.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: March 31, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • TAPE HEATING METHODS
    Publication number: 20200090974
    Abstract: Implementations of a method of increasing the adhesion of a tape. Implementations may include: mounting a tape to a frame, mounting a substrate to the tape, heating the tape after mounting the substrate at one or more temperatures for a predetermined period of time, and increasing an adhesion of the tape to the substrate through heating the tape.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 19, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • JET ABLATION DIE SINGULATION SYSTEMS AND RELATED METHODS
    Publication number: 20200091000
    Abstract: Implementations of a method singulating a plurality of semiconductor die. Implementations may include: forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate where the semiconductor substrate includes a plurality of semiconductor die. The method may include etching substantially through a thickness of the semiconductor substrate at the pattern in the back metal layer and jet ablating a layer of passivation material coupled to a second side of the semiconductor substrate to singulate the plurality of semiconductor die.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 19, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. SEDDON
  • Semiconductor substrate crack mitigation systems and related methods
    Patent number: 10593602
    Abstract: Implementations of a method for healing a crack in a semiconductor substrate may include identifying a crack in a semiconductor substrate and heating an area of the semiconductor substrate including the crack until the crack is healed.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 17, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Absolute and differential pressure sensors and related methods
    Patent number: 10589989
    Abstract: Implementations of absolute pressure sensor devices may include a microelectromechanical system (MEMS) absolute pressure sensor coupled over a controller die. The MEMS absolute pressure sensor may be mechanically coupled to the controller die and may also be configured to electrically couple with the controller die. A perimeter of the controller die may be one of the same size and larger than a perimeter of the MEMS absolute pressure sensor. The controller die may be configured to electrically couple with a module through an electrical connector.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: March 17, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • CURRENT SENSOR PACKAGES WITH THROUGH HOLE IN SEMICONDUCTOR
    Publication number: 20200066970
    Abstract: A semiconductor package includes a semiconductor die. A through hole in the semiconductor package and semiconductor die extends from one side of the semiconductor package and die to an opposite side of the semiconductor package and die. The through hole is configured to receive a current-carrying conductor there through. At least one current sensor is formed in, or on, the semiconductor die and configured to sense current flow in the current-carrying conductor received in the through hole.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. HALL, Michael J. SEDDON, Yenting WEN