Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.

Abstract: A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

Abstract: Implementations of a method singulating a plurality of semiconductor die. Implementations may include: forming a pattern in a back metal layer coupled on a first side of a semiconductor substrate where the semiconductor substrate includes a plurality of semiconductor die. The method may include etching substantially through a thickness of the semiconductor substrate at the pattern in the back metal layer and jet ablating a layer of passivation material coupled to a second side of the semiconductor substrate to singulate the plurality of semiconductor die.

Abstract: A method for forming a through-substrate via structure includes providing a substrate and providing a conductive via structure adjacent to a first surface of the substrate. The method includes providing a recessed region on an opposite surface of the substrate towards the conductive via structure. The method includes providing an insulator in the recessed region and providing a conductive region extending along a first sidewall surface of the recessed region in the cross-sectional view. In some examples, the first conductive region is provided to be coupled to the conductive via structure and to be further along at least a portion of the opposite surface of the substrate outside of the recessed region. The method includes providing a protective structure within the recessed region over a first portion of the first conductive region but not over a second portion of the first conductive region that is outside of the recessed region.

Abstract: A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.

Abstract: A semiconductor wafer has a base material. The semiconductor wafer may have an edge support ring. A grinding phase of a surface of the semiconductor wafer removes a portion of the base material. The grinder is removed from or lifted off the surface of the semiconductor wafer during a separation phase. The surface of the semiconductor wafer and under the grinder is rinsed during the grinding phase and separation phase to remove particles. A rinsing solution is dispensed from a rinsing solution source to rinse the surface of the semiconductor wafer. The rinsing solution source can move in position while dispensing the rinsing solution to rinse the surface of the semiconductor wafer. The grinding phase and separation phase are repeated during the entire grinding operation, when grinding conductive TSVs, or during the final grinding stages, until the final thickness of the semiconductor wafer is achieved.

Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and forming a groove at the pattern of the photoresist layer only partially through a thickness of the backside metal layer. The groove may be located in the die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the photoresist layer, and singulating the plurality of die included in the substrate by removing substrate material in the die street.

Abstract: Implementations of a method of increasing the adhesion of a tape. Implementations may include: mounting a tape to a frame, mounting a substrate to the tape, heating the tape after mounting the substrate at one or more temperatures for a predetermined period of time, and increasing an adhesion of the tape to the substrate through heating the tape.

Abstract: Implementations of methods of thinning a semiconductor substrate may include: providing a semiconductor substrate having a first surface and a second surface opposing the first surface, the semiconductor substrate having a thickness between the first surface and the second surface. The method may further include inducing damage into a portion of the semiconductor substrate at a first depth into the thickness forming a first damage layer, inducing damage into a portion of the semiconductor substrate at a second depth into the thickness forming a second damage layer, and applying ultrasonic energy to the semiconductor substrate. The method may include separating the semiconductor substrate into three separate thinned portions across the thickness along the first damage layer and along the second damage layer.

Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and etching through the backside metal layer located in the die street of the substrate. The substrate may be exposed through the etch. The method may also include singulating the plurality of die included in the substrate through removing a substrate material in the die street.

Abstract: Implementations of methods of cutting a semiconductor substrate may include aligning a first saw blade substantially perpendicularly with a crystal plane of a non-cubic crystalline lattice of a semiconductor substrate coupled with a backmetal layer and cutting through at least a majority of the semiconductor substrate at an angle substantially perpendicular with the crystal plane of the non-cubic crystalline lattice of the semiconductor substrate. The method may also include aligning a second saw blade substantially perpendicularly with the semiconductor substrate and cutting entirely through the semiconductor substrate and the backmetal layer using the second saw blade.

Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include exposing a substrate material of a substrate in a die street through removing a metal layer in the die street coupled to the substrate, wherein only a portion of the substrate material in the die street is removed, and singulating a plurality of die included in the substrate through plasma etching the exposed substrate material of the substrate in the die street.

Abstract: A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.

Abstract: Implementations of a method of singulating a plurality of semiconductor die may include forming an opening in a layer of passivation material coupled to a second side of a semiconductor substrate; etching substantially through a thickness of the semiconductor substrate at the opening in the layer of passivation material to form etched sidewalls along the thickness at a plurality of die streets; and jet ablating one or more portions of the layer of passivation material that overhangs the etched sidewalls.

Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a seed layer on a second side of a substrate opposite the first side of the substrate, using a shadow mask, applying a mask layer over the seed layer, forming a backside metal layer over the seed layer, removing the mask layer, and singulating the plurality of die included in the substrate through removing substrate material in the die street and through removing seed layer material in the die street.

Abstract: Implementations of a semiconductor package may include a semiconductor die including a first side and a second side where the first side of the semiconductor die includes one or more electrical contacts; a layer of metal coupled to the second side of the semiconductor; and a stress balance structure coupled to one of the layer of metal or around the one or more electrical contacts.

Abstract: Implementations of a method for aligning a semiconductor wafer for singulation may include: providing a semiconductor wafer having a first side and a second side. The first side of the wafer may include a plurality of die and the plurality of die may be separated by streets. The semiconductor wafer may include an edge ring around a perimeter of the wafer on the second side of the wafer. The wafer may also include a metal layer on the second side of the wafer. The metal layer may substantially cover the edge ring. The method may include grinding the edge ring to create an edge exclusion area and aligning the semiconductor wafer with a saw using a camera positioned in the edge exclusion area on the second side of the wafer. Aligning the wafer may include using three or more alignment features included in the edge exclusion area.

Abstract: A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

Abstract: Implementations of methods of singulating a plurality of die comprised in a substrate may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a polymer layer over the backside metal layer and forming a groove entirely through the polymer layer and partially through a thickness of the backside metal layer. The groove may be located in a die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the polymer layer, singulating the plurality of die in the substrate by removing substrate material in the die street.