Abstract: A pixel circuit for a display device includes a drive transistor configured to control an amount of current to a light-emitting device depending upon a voltage applied to a gate of the drive transistor; a second transistor connected to the gate of the drive transistor and a second terminal of the drive transistor such that, when the second transistor is in an on state the drive transistor becomes diode-connected such that the gate and a second terminal of the drive transistor are connected through the second transistor; a light-emitting device that is connected at a first node to the second terminal of the drive transistor and at a second node to a first voltage supply; a third transistor that is connected between an initialization voltage supply and the first node of the light-emitting device, wherein a node N1 is a connection of the second terminal of the drive transistor, the first node of the light-emitting device, and the third transistor; and at least one capacitor having a first plate that is connected

Abstract: A pixel circuit for a display device includes a drive transistor configured to control an amount of current to a light-emitting device during an emission phase depending upon a voltage applied to a gate of the drive transistor; a second transistor connected to the gate of the drive transistor, wherein the second transistor is in an on state during a combined programming and compensation phase and in an off state during the emission phase, and when the second transistor is in an on state the drive transistor becomes diode-connected such that a gate and a second terminal of the drive transistor are connected through the second transistor; a third transistor connected to the second terminal of the drive transistor, wherein the third transistor is in an on state during the combined programming and compensation phase to permit a reference current to be applied through the drive transistor, and is in an off state during the emission phase to remove the reference current; and a capacitor having a first plate that is

Abstract: A pixel circuit for a display device includes a drive transistor configured to control an amount of current to a light-emitting device depending upon a voltage applied to a gate of the drive transistor; a second transistor connected to the gate of the drive transistor and a second terminal of the drive transistor, such that when the second transistor is in an on state the drive transistor becomes diode-connected such that the gate and the second terminal of the drive transistor are connected through the second transistor; a light-emitting device that is connected at a first node to a third terminal of the drive transistor and at a second node to a first voltage supply; a third transistor connected to the first node of the light-emitting device, which connects a data voltage to the first node of the light-emitting device; a fourth transistor that is connected between the second terminal of the drive transistor and a second voltage supply; and at least one capacitor having a first plate that is connected to the

Abstract: A display system includes a display panel comprising a plurality of pixel circuits, and a measurement and data processing unit that is external to the display panel. Each pixel circuit includes a light-emitting device having a first terminal connected to a first voltage supply and a second terminal opposite from the first terminal; a first transistor connected between a data voltage supply line from the measurement and data processing unit and the second terminal of the light emitting device; and a second transistor connected between the second terminal of the light-emitting device and a sample line to the measurement and data processing unit. The measurement and data processing unit is configured to sample a measured voltage at the second terminal of the light-emitting device through the sample line and to output a data voltage to the light-emitting device based on the measured voltage to compensate variations in properties of the light-emitting device.

Abstract: A pixel circuit for a display device includes a drive transistor configured to control an amount of current to a light-emitting device depending upon a voltage applied to a gate of the drive transistor; a second transistor connected to the gate of the drive transistor and a second terminal of the drive transistor such that, when the second transistor is in an on state the drive transistor becomes diode-connected such that the gate and a second terminal of the drive transistor are connected through the second transistor; a light-emitting device that is connected at a first node to the second terminal of the drive transistor and at a second node to a first voltage supply; a third transistor that is connected between an initialization voltage supply and the first node of the light-emitting device, wherein a node N1 is a connection of the second terminal of the drive transistor, the first node of the light-emitting device, and the third transistor; and at least one capacitor having a first plate that is connected

Abstract: A pixel circuit for a display device includes a drive transistor configured to control an amount of current to a light-emitting device during an emission phase depending upon a voltage applied to a gate of the drive transistor; a second transistor connected to the gate of the drive transistor, wherein the second transistor is in an on state during a combined programming and compensation phase and in an off state during the emission phase, and when the second transistor is in an on state the drive transistor becomes diode-connected such that a gate and a second terminal of the drive transistor are connected through the second transistor; a third transistor connected to the second terminal of the drive transistor, wherein the third transistor is in an on state during the combined programming and compensation phase to permit a reference current to be applied through the drive transistor, and is in an off state during the emission phase to remove the reference current; and a capacitor having a first plate that is

Abstract: A pixel circuit for a display device includes a drive transistor configured to control an amount of current to a light-emitting device depending upon a voltage applied to a gate of the drive transistor; a second transistor connected to the gate of the drive transistor and a second terminal of the drive transistor, such that when the second transistor is in an on state the drive transistor becomes diode-connected such that the gate and the second terminal of the drive transistor are connected through the second transistor; a light-emitting device that is connected at a first node to a third terminal of the drive transistor and at a second node to a first voltage supply; a third transistor connected to the first node of the light-emitting device, which connects a data voltage to the first node of the light-emitting device; a fourth transistor that is connected between the second terminal of the drive transistor and a second voltage supply; and at least one capacitor having a first plate that is connected to the

Abstract: A method of determining the result of an assay in a microfluidic device includes the steps of: dispensing a sample droplet onto a first portion of an electrode array of the microfluidic device; dispensing a reagent droplet onto a second portion of the electrode array of the microfluidic device; controlling actuation voltages applied to the electrode array to mix the sample droplet and the reagent droplet into a product droplet; sensing a dynamic property of the product droplet; and determining an assay of the sample droplet based on the sensed dynamic property. The dynamic property is a physical property of the product droplet that influences a transport property of the product droplet on the electrode array. Example dynamic properties of the product droplet include the moveable state, split-able state, and viscosity based on droplet properties. The method may be used to perform an amoebocyte lysate (LAL) assay.

Abstract: A method of determining the result of an assay in a microfluidic device includes the steps of: dispensing a sample droplet onto a first portion of an electrode array of the microfluidic device; dispensing a reagent droplet onto a second portion of the electrode array of the microfluidic device; controlling actuation voltages applied to the electrode array to mix the sample droplet and the reagent droplet into a product droplet; sensing a dynamic property of the product droplet; and determining an assay of the sample droplet based on the sensed dynamic property. The dynamic property is a physical property of the product droplet that influences a transport property of the product droplet on the electrode array. Example dynamic properties of the product droplet include the moveable state, split-able state, and viscosity based on droplet properties. The method may be used to perform an amoebocyte lysate (LAL) assay.

Abstract: A charge storage circuit for a pixel comprises a charge storage node. First and second series-connected transistors (8,10) are provided for selectively isolating the charge storage node from a first voltage input (9,SL) for supplying a data voltage. The circuit is provided with a voltage follower circuit for replicating a voltage at the charge storage node (12) at another node in the circuit thereby to reduce the drain-source voltage across the second transistor (10). The first transistor forms part of the voltage follower circuit.

Abstract: In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

Abstract: In one embodiment of the present invention, a wireless interface is provided for supplying all signals and power exclusively wirelessly from a transmitting section to a receiving section. The transmitting section includes a transmitter arranged to modulate a carrier with signals, such as data, control and timing signals. The transmitter is connected to a transmit antenna which comprises a parallel resonant circuit in series with a series resonant circuit. The parallel and series resonant circuits include inductors which are inductively coupled to an inductor of a receive antenna in the receiving section.

Abstract: A charge storage circuit for a pixel comprises a charge storage node. First and second series-connected transistors (8,10) are provided for selectively isolating the charge storage node from a first voltage input (9,SL) for supplying a data voltage. The circuit is provided with a voltage follower circuit for replicating a voltage at the charge storage node (12) at another node in the circuit thereby to reduce the drain-source voltage across the second transistor (10). The first transistor forms part of the voltage follower circuit.

Abstract: The present invention relates to an operation apparatus including an operation terminal used for operating a domestic apparatus near a wall surface. An operation host section (20) includes a module of an accessing function element and electric supply function element, which module discharges an operation signal in the air, or includes a member in which such a module is disposed in an array form. Power supply in a non-contact manner and transmission of an operation signal in a wireless manner are carried out between the operation terminal and the operation host section. The operation terminal is easily adhered extremely thin onto the wall and allows providing an operation function without providing any physical wiring. Further, few electricity is wasted, and operation is possible under conserved energy. Hence, an operation system is provided which uses an operation terminal having low security risks while achieving flexibility in its layout.

Abstract: There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

Abstract: A display device is provided, including a signal transmission mechanism that makes it possible to reduce the number of pins on an FPC board connected to a TFT substrate or eliminate the necessity for the FPC board, and that can be readily applied to a compact device. The present liquid crystal display device includes light detectors, a receiver circuit, a display control circuit, a video signal line drive circuit, a scanning signal line drive circuit, and a display portion, which are formed on a TFT substrate of a liquid crystal display panel, and it also includes white LEDs, and an LED drive circuit, which are included in a backlight portion. The LED drive circuit drives the white LEDs, each emitting a light (modulation) signal LS in accordance with an externally-provided video signal VS. The receiver circuit generates (demodulates) the video signal VS based on a signal received via the light detector.

Abstract: In one embodiment of the present invention, a wireless interface is provided for supplying all signals and power exclusively wirelessly from a transmitting section to a receiving section. The transmitting section includes a transmitter arranged to modulate a carrier with signals, such as data, control and timing signals. The transmitter is connected to a transmit antenna which comprises a parallel resonant circuit in series with a series resonant circuit. The parallel and series resonant circuits include inductors which are inductively coupled to an inductor of a receive antenna in the receiving section.

Abstract: An integrated MEMS package and associated packaging method are provided. The method includes: forming an electrical circuit, electrically connected to the first substrate; integrating a MEMS device on a first substrate region, electrically connected to the first substrate; providing a second substrate overlying the first substrate; and, forming a wall along the first region boundaries, between the first and second substrate. In one aspect, the electrical circuit is formed using thin-film processes; and, wherein integrating the MEMS device on the first substrate region includes forming the MEMS using thin-film processes, simultaneous with the formation of the electrical device. Alternately, the MEMS device is formed in a separate process, attached to the first substrate, and electrical interconnections are formed to the first substrate using thin-film processes.

Abstract: A data signal line drive circuit is provided with first sampling portions, and second sampling portions operated at a lower speed. By the action of selection circuits, the first sampling portions are operated during a normal display mode, and the second sampling portions are operated during a partial display mode. To ensure a correct sampling operation, one line time and a sampling interval are rendered longer during a display period of the partial display mode than during the normal display mode. During the normal display mode, both the first sampling portions and the second sampling portions may be operated. Thus, power consumption of a liquid crystal display device during the partial display is reduced.

Abstract: In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.