Abstract: A matrix type image display device has a structure in which the internal states of all of shift registers (the outputs of flip-flops included in the shift registers) in a scanning signal line drive circuit and data signal line drive circuit are made inactive by the use of an initializing signal generated by a NAND gate based on a combination of signals, which do not affect a displayed image, from a control circuit. With this structure, since the shift registers are initialized when power is supplied, it is possible to prevent an indefinite state when power is supplied. Therefore, by selectively inputting signals (such as clock signals) for controlling the shift registers, it is possible to prevent an excessive increase in the signal line load. Consequently, the operation of the image display device can be stabilized.

Abstract: A digital-to-analog converter includes a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit including switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during the precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.

Abstract: A precharge control circuit constituted by (1) a latch circuit mounted in a precharge circuit and (2) a level shifter circuit of a current drive type controlled through an output of the latch circuit is included. The precharge control circuit changes the latch circuit to an active state to cause the level shifter circuit of a current drive type to operate only during a precharge period and also during immediately preceding and succeeding periods, and outside these periods, changes the latch circuit in a non-active state and the level shifter circuit of a current drive type in an operating state to save power consumption in the level shifter circuit. This enables a low-power-consuming precharge circuit, as well as a low-power-consuming image display device with a high quality display capability, to be offered.

Abstract: A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.

Abstract: There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

Abstract: A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.

Abstract: An active matrix device comprises an array of picture elements. Each picture element has an image element, such as an LCD cell (11) connected to a first storage capacitor 12 and arranged to be connected to a data line 4 by an thin film transistor 10 when activated by a scan signal on a scan line 6. A second storage capacitor 21 can be connected across the first capacitor 12 by means of another thin film transistor 20 when desired so as to increase the storage capacitance at the pixel.

Abstract: A frame rate controller 20 is provided for controlling the frame refresh rate of an active matrix display. The controller 20 comprises a first circuit such as a preloadable synchronous counter 21 which counts vertical synchronization signals VSYNC and supplies an enable signal FE for every Nth frame of data, where N is an integer greater than zero and is selectable. A gating arrangement 26 is controlled by the enable signal FE so that an active matrix display is refreshed for every Nth frame of data, thus allowing a reduction in power consumption of the display.

Abstract: Multi-format sampling registers, digital to analogue converters, data drivers and active matrix displays are provided which provide power saving in lower resolution formats by disabling circuitry which is not required in those formats.

Abstract: An active matrix device includes a data line driver circuit for sampling the input signal to produce data signals for each of the rows of control elements in a corresponding line period, and a scan line driver circuit for addressing the scan lines sequentially by applying a scan signal to the scan inputs of the control elements along each of the rows so as to supply said data signals to the control elements along the row. Such circuits are controlled so that a data input signal is sampled and stored to produce data signals for a first group of the control elements along the row in a first line subperiod and the stored data signals are applied to the first group of control elements in a second line subperiod, and so that the data input signal is sampled and stored to produce data signals for a second group of control elements along the row in the second line subperiod and the stored data signals are applied to the second group of control elements in a subsequent line subperiod.

Abstract: An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.

Abstract: A level-shifting pass gate comprises a field effect transistor (M1) whose source is connected to a signal input (IN) and whose drain is connected to a signal output (OUT). A load (R) is connected between the drain of the transistor (M1) and a supply line (vdd). A control means (1) has an enable input (EN) which receives signals for enabling or disabling the pass gate. When the gate is enabled, the control means (1) controls the transistor (M1) and possibly the load (R) so that an input logic low level is passed substantially unchanged whereas a relatively low input high level is shifted to a higher output logic high level approaching the supply voltage. When the pass gate is disabled, the transistor (M1) is switched off so that the input (IN) is isolated from the output (OUT) and assumes a high impedance state. Conversely, when disabled, the output (OUT) defaults to a predetermined state, such as logic low, logic high or high impedance.

Abstract: A static clock pulse generator comprises a plurality of stages, each of which comprises a reset-set flip-flop and a gating circuit. Complementary outputs of the flip-flop control the gating circuit for supplying clock pulses from a clock input to the output of the stage. When the gating circuit is switched off, it holds the output at a default level. The flip-flop has a set input which receives the output from the preceding stage and a reset input which receives the output from the following stage.

Abstract: A static clock pulse generator comprises a plurality of stages 1,2, each of which comprises a D-type flip-flop 3 and a gating circuit 4. The flip-flop 3 supplies output signals Q of the stage which are also used as gating signals for the gating circuit 4 of the following stage. The gating circuit 4 supplies a signal to the data input D of the flip-flop 3 when its gating input G is active and a clock pulse is present on the clock input CK or !CK. An asynchronous reset signal R is supplied to the flip-flop 3 from the following stage.

Abstract: A digital-to-analog converter comprises a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit comprising switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during a precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.

Abstract: A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gates of the transistors T1 and T2 receive a shifted version of the direct input signal IN from a source-follower comprising the transistors T3 and T4.

Abstract: An active matrix display comprises an active matrix 1 and a digital data driver 30 formed on a common substrate 100 by a common integration process. The driver 30 comprises a serial to parallel converter 20 having m registers forming at least one set for storing display data for m picture elements, where m is less than the number M of data lines of the matrix 1. The outputs of the registers are connected to m digital/analogue converters 21 whose outputs are connected to m bus lines 50 of an m phase analogue driver 22 in the form of a switching network. The switching network connects in turn groups of m physically adjacent data lines of the matrix 1 to the m bus line, respectively.

Abstract: Multi-format sampling registers, digital to analogue converters, data drivers and active matrix displays are provided which provide power saving in lower resolution formats by disabling circuitry which is not required in those formats.

Abstract: A driving arrangement for an active matrix liquid crystal display comprises: (a) a multi-format digital data driver arranged to operate in a plurality of different display modes, to receive digital input data in a plurality of different formats, and to drive data lines of the liquid crystal display so as to cause an image to be displayed in the display corresponding to said input data; and (b) data analysis means arranged to receive said digital input data, to determine the format of the input data, and to control the data driver to operate in the display mode corresponding to the format of the input data. There is provided a method of reducing power required to display a sequence of images on a liquid crystal display, in which images are analysed and if consecutive Images are substantially the same, then the liquid crystal display is not updated with the subsequent image.

Abstract: A static clock pulse generator comprises a plurality of stages 1,2, each of which comprises a D-type flip-flop 3 and a gating circuit 4. The flip-flop 3 supplies output signals Q of the stage which are also used as gating signals for the gating circuit 4 of the following stage. The gating circuit 4 supplies a signal to the data input D of the flip-flop 3 when its gating input G is active and a clock pulse is present on the clock input CK or !CK. An asynchronous reset signal R is supplied to the flip-flop 3 from the following stage.