Patents by Inventor Michael James Brownlow
Michael James Brownlow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7420402Abstract: A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics are switched according to High/Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON/OFF characteristics are switched according to High/Low of the reset signal.Type: GrantFiled: January 27, 2005Date of Patent: September 2, 2008Assignee: Sharp Kabushiki KaishaInventors: Hajime Washio, Yuhichiroh Murakami, Michael James Brownlow
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Publication number: 20080150924Abstract: There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.Type: ApplicationFiled: February 21, 2008Publication date: June 26, 2008Applicant: Sharp Kabushiki KaishaInventors: Hidehiko Yamashita, Hajime Washio, Yasushi Kubota, Graham Andrew Cairns, Michael James Brownlow
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Patent number: 7365727Abstract: A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease.Type: GrantFiled: February 25, 2004Date of Patent: April 29, 2008Assignee: Sharp Kabushiki KaishaInventors: Masakazu Satoh, Yasushi Kubota, Hajime Washio, Kazuhiro Maeda, Michael James Brownlow, Graham Andrew Cairns
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Patent number: 7358950Abstract: There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.Type: GrantFiled: May 16, 2002Date of Patent: April 15, 2008Assignee: Sharp Kabushiki KaishaInventors: Hidehiko Yamashita, Hajime Washio, Yasushi Kubota, Graham Andrew Cairns, Michael James Brownlow
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Patent number: 7339570Abstract: An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.Type: GrantFiled: May 9, 2001Date of Patent: March 4, 2008Assignee: Sharp Kabushiki KaishaInventors: Yasushi Kubota, Hajime Washio, Michael James Brownlow, Graham Andrew Cairns, Yasuyoshi Kaise, Kazuhiro Maeda
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Patent number: 7217588Abstract: An integrated MEMS package and associated packaging method are provided. The method includes: forming an electrical circuit, electrically connected to the first substrate; integrating a MEMS device on a first substrate region, electrically connected to the first substrate; providing a second substrate overlying the first substrate; and, forming a wall along the first region boundaries, between the first and second substrate. In one aspect, the electrical circuit is formed using thin-film processes; and, wherein integrating the MEMS device on the first substrate region includes forming the MEMS using thin-film processes, simultaneous with the formation of the electrical device. Alternately, the MEMS device is formed in a separate process, attached to the first substrate, and electrical interconnections are formed to the first substrate using thin-film processes.Type: GrantFiled: July 8, 2005Date of Patent: May 15, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: John W. Hartzell, Harry Garth Walton, Michael James Brownlow
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Patent number: 7212184Abstract: In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. Moreover, two kinds of clock signals, each of which has a duty ratio of not more than 50% and which have no overlapped portions in their low-level periods, are used so as to prevent the outputs of the shift-register from overlapping each other. Thus, it is possible to provide a shift register which is preferably used for a driving circuit of an image display device, can miniaturize the driving circuit, and can desirably change the pulse width of the output signal, and also to provide an image display device using such a shift register.Type: GrantFiled: March 12, 2004Date of Patent: May 1, 2007Assignee: Sharp Kabushiki KaishaInventors: Hajime Washio, Yasushi Kubota, Kazuhiro Maeda, Yasuyoshi Kaise, Michael James Brownlow, Graham Andrew Cairns
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Patent number: 7190338Abstract: An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.Type: GrantFiled: March 25, 2005Date of Patent: March 13, 2007Assignee: Sharp Kabushiki KaishaInventors: Yasushi Kubota, Hajime Washio, Michael James Brownlow, Graham Andrew Cairns, Yasuyoshi Kaise, Kazuhiro Maeda
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Patent number: 7042433Abstract: A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring.Type: GrantFiled: May 9, 2000Date of Patent: May 9, 2006Assignee: Sharp Kabushiki KaishaInventors: Yasushi Kubota, Hajime Washio, Kazuhiro Maeda, Graham Andrew Cairns, Michael James Brownlow
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Patent number: 6970163Abstract: A frame rate controller (20) is provided for controlling the frame refresh rate of an active matrix display. The controller (20) comprises a first circuit such as a preloadable synchronous counter (21) which counts vertical synchronization signals VSYNC and supplies an enable signal FE for every Nth frame of data, where N is an integer greater than zero and is selectable. A gating arrangement (26) is controlled by the enable signal FE so that an active matrix display is refreshed for every Nth frame of data, thus allowing a reduction in power consumption of the display.Type: GrantFiled: March 5, 2002Date of Patent: November 29, 2005Assignee: Sharp Kabushiki KaishaInventors: Graham Andrew Cairns, Michael James Brownlow
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Patent number: 6952244Abstract: An active matrix devise comprises an array of picture elements. Each picture element has an image element, such as an LCD cell (11) connected to a first storage capacitor 12 and arranged to be connected to a data line 4 by an thin film transistor 10 when activated by a scan signal on a scan line 6. A second storage capacitor 21 can be connected across the first capacitor 12 by means of another thin film transistor 20 when desired so as to increase the storage capacitance at the pixel.Type: GrantFiled: February 20, 2002Date of Patent: October 4, 2005Assignee: Sharp Kabushiki KaishaInventors: Graham Andrew Cairns, Catherine Rosinda Marie Armida Dachs, Michael James Brownlow, Yasuyoshi Kaise
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Patent number: 6909417Abstract: A level shifter 13 is provided for each of SR flip flops F1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifter 13, and the operation is suspended at the end of the pulse output. Thus, the level shifters 13 can operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop F1. As a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.Type: GrantFiled: May 25, 2000Date of Patent: June 21, 2005Assignee: Sharp Kabushiki KaishaInventors: Hajime Washio, Yasushi Kubota, Kazuhiro Maeda, Yasuyoshi Kaise, Michael James Brownlow, Graham Andrew Cairns
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Patent number: 6836269Abstract: A precharge control circuit constituted by (1) a latch circuit mounted in a precharge circuit and (2) a level shifter circuit of a current drive type controlled through an output of the latch circuit is included. The precharge control circuit changes the latch circuit to an active state to cause the level shifter circuit of a current drive type to operate only during a precharge period and also during immediately preceding and succeeding periods, and outside these periods, changes the latch circuit in a non-active state and the level shifter circuit of a current drive type in an operating state to save power consumption in the level shifter circuit. This enables a low-power-consuming precharge circuit, as well as a low-power-consuming image display device with a high quality display capability, to be offered.Type: GrantFiled: February 28, 2001Date of Patent: December 28, 2004Assignee: Sharp Kabushiki KaishaInventors: Kazuhiro Maeda, Hajime Washio, Yasushi Kubota, Yasuyoshi Kaise, Michael James Brownlow, Graham Andrew Cairns
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Patent number: 6806854Abstract: An active matrix display comprises an active matrix 1 and a digital data driver 30 formed on a common substrate 100 by a common integration process. The driver 30 comprises a serial to parallel converter 20 having m registers forming at least one set for storing display data for m picture elements, where m is less than the number M of data lines of the matrix 1. The outputs of the registers are connected to m digital/analogue converters 21 whose outputs are connected to m bus lines 50 of an m phase analogue driver 22 in the form of a switching network. The switching network connects in turn groups of m physically adjacent data lines of the matrix 1 to the m bus line, respectively.Type: GrantFiled: September 4, 2001Date of Patent: October 19, 2004Assignee: Sharp Kabushiki KaishaInventors: Graham Andrew Cairns, Michael James Brownlow
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Publication number: 20040183771Abstract: A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease.Type: ApplicationFiled: February 25, 2004Publication date: September 23, 2004Inventors: Masakazu Satoh, Yasushi Kubota, Hajime Washio, Kazuhiro Maeda, Michael James Brownlow, Graham Andrew Cairns
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Publication number: 20040174334Abstract: In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. Moreover, two kinds of clock signals, each of which has a duty ratio of not more than 50% and which have no overlapped portions in their low-level periods, are used so as to prevent the outputs of the shift-register from overlapping each other. Thus, it is possible to provide a shift register which is preferably used for a driving circuit of an image display device, can miniaturize the driving circuit, and can desirably change the pulse width of the output signal, and also to provide an image display device using such a shift register.Type: ApplicationFiled: March 12, 2004Publication date: September 9, 2004Inventors: Hajime Washio, Yasushi Kubota, Kazuhiro Maeda, Yasuyoshi Kaise, Michael James Brownlow, Graham Andrew Cairns
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Patent number: 6724363Abstract: A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease.Type: GrantFiled: May 11, 2000Date of Patent: April 20, 2004Assignee: Sharp Kabushiki KaishaInventors: Masakazu Satoh, Yasushi Kubota, Hajime Washio, Kazuhiro Maeda, Michael James Brownlow, Graham Andrew Cairns
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Patent number: 6724361Abstract: In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. An output pulse having the same width as the pulse of the clock signal is generated.Type: GrantFiled: November 1, 2000Date of Patent: April 20, 2004Assignee: Sharp Kabushiki KaishaInventors: Hajime Washio, Yasushi Kubota, Kazuhiro Maeda, Yasuyoshi Kaise, Michael James Brownlow, Graham Andrew Cairns
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Publication number: 20030174115Abstract: A level shifter 13 is provided for each of SR flip flops F1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifter 13, and the operation is suspended at the end of the pulse output. Thus, the level shifters 13 can operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop F1. As a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.Type: ApplicationFiled: May 25, 2000Publication date: September 18, 2003Inventors: Hajime Washio, Yasushi Kubota, Kazuhiro Maeda, Yasuyoshi Kaise, Michael James Brownlow, Graham Andrew Cairns
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Patent number: 6617878Abstract: A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.Type: GrantFiled: August 9, 2002Date of Patent: September 9, 2003Assignee: Sharp Kabushiki KaishaInventors: Michael James Brownlow, Graham Andrew Cairns, Yasushi Kubota, Hajime Washio