Abstract: A device that includes: (i) an evaluated circuit; (ii) a leakage current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a leakage current of the evaluated circuit; (iii) a switching current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a switching induced current of the evaluated circuit; (iv) a power reduction module that is configured to: (a) compare between an oscillation frequency of the leakage current dependent oscillator and an oscillation frequency of the switching current dependent oscillator, to provide a current comparison result; (b) select a power reduction technique out of a dynamic voltage and frequency scaling technique and a power gating technique in view of the current comparison result; and (c) apply the selected power reduction technique.

Abstract: A method for generating a clock signal and a device having clock generating capabilities, the device includes: (i) a first divider, adapted to receive an input clock signal and divide the input clock signal to provide a first clock signal; (ii) a second divider, adapted to receive an input clock signal and divide the input clock signal to provide a second clock signal; wherein the first clock signal is phase shifted in relation to the second clock signal by half an input clock cycle; wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of delay affecting parameter values; (iii) a reconstruction circuit, connected to the first and second divider circuits, adapted to receive the first and second clock signals and apply a logical operation on the first and second clock signals to provide a reconstructed clock signal; and (iv) a selection circuit, connected to the first divider, second divider and reconstruction circuit, adapted to output an outp

Abstract: A method (1000) for sharing charge between IO circuits, the method (1000) includes providing (1010) an integrated circuit that comprises multiple IO circuits, each comprising an IO pad. The method (1000) is characterized by including: determining (1020) to share a charge between multiple IO circuits; and sharing charge (1030) between the multiple IO circuits by coupling the multiple IO circuits to a shared circuit that is characterized by a state that reflects multiple iterations of sharing charge operations.

Abstract: A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests.

Abstract: A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting a timing error; delaying by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining a clock signal frequency and a level of the supply voltage in response to at least one detected timing error.

Abstract: A device and a method for generating a output clock signal having a output cycle, the method includes: (i) adjusting a delay of an adjustable ring oscillator to provide a high frequency clock signal having a short cycle so that the output cycle substantially equals a sum of integer multiples of a sleep cycle and integer multiplies of the short cycle; wherein the output cycle differs from any integer multiples of the sleep cycle; wherein the sleep cycle characterizes a sleep clock signal that is generated by a low frequency sleep clock; wherein the short cycle is shorter than the sleep cycle; (ii) counting short cycles and sleep cycles; and (iii) generating, during a sleep mode, in response to the counting and to a predefined counting pattern, the first clock signal; wherein the generating includes activating the adjustable ring oscillator only during a portion of a single sleep cycle per each output cycle.

Abstract: A system, that includes: a memory unit adapted to store state duration statistics indicative of possible low power state durations and probabilities associates with the possible state durations; and a power controller, adapted to: receive a request to cause a circuit to enter a next state, and assist in causing the circuit to enter the next state if during a delay period that follows a reception of the request the power controller does not receive a request to cause the circuit to exit the next state; wherein the delay period is determined in response to: (i) the next state duration statistics, (ii) power saving gained from entering the next state; and (iii) power penalty associated with entering the next state and exiting the next state.

Abstract: A method for generating a clock signal and a device having clock generating capabilities, the device includes: (i) a first divider, adapted to receive an input clock signal and divide the input clock signal to provide a first clock signal; (ii) a second divider, adapted to receive an input clock signal and divide the input clock signal to provide a second clock signal; wherein the first clock signal is phase shifted in relation to the second clock signal by half an input clock cycle; wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of delay affecting parameter values; (iii) a reconstruction circuit, connected to the first and second divider circuits, adapted to receive the first and second clock signals and apply a logical operation on the first and second clock signals to provide a reconstructed clock signal; and (iv) a selection circuit, connected to the first divider, second divider and reconstruction circuit, adapted to output an outp

Abstract: A method for evaluating a quiescent current, the method includes: measuring, when a module is at a first mode, a first voltage drop on a first resistor that is coupled between a supply pin of an integrated circuit that comprises the module and a first test pin of the integrated circuit; assessing, when the module is at a second mode, a second voltage drop on a second resistor that is coupled between the supply pin and a second test pin of the integrated circuit; and evaluating a quiescent current of the module in response to the first and second voltage drops; wherein expected values of quiescent current of the module differ from one mode to the other; and wherein a resistance of the first resistor differs from the resistance of the second resistor.

Abstract: A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module; and providing a secured real time clock signal when the multiple input ports of the secured real time clock module are locked and when the multiple input ports of the secured real time clock module are unlocked; wherein changes in a supply voltage results in a supply voltage induced changes of an input signal provided to an input port of the secured real time clock module; wherein a maximal frequency of the supply voltage induced changes of the input signal is lower then the high frequency of the predefined high frequency code.

Abstract: A device having timing error management capabilities and a method for timing error management. The device includes a first input node adapted to receive input data; a first latch, a second latch and a comparator, rising a first multiplexer and a second multiplexer; wherein the second multiplexer is adapted to provide input data to the second latch from the first input mode during a first operational mode of the device and to provide a first latch output signal to the second latch during a second operational mode; wherein the comparator is adapted to compare, during a first clock phase, between the first latch output signal and between a second latch output signal and in response to the comparison selectively generate an error signal.

Abstract: A method for race prevention and a device that has race prevention capabilities. The method includes: selectively providing data or scan data to a input latching logic, activating the input latching logic for a first scan mode activation period, introducing a substantial time shift between the first scan mode activation period and a second scan mode activation period, and activating a output latching logic, connected to the input latching logic for a second scan mode activation period. The device includes: an interface logic, a input latching logic, a output latching logic and a control logic. The interface logic is adapted to selectively provide data or scan data to the input latching logic. The control logic is adapted to introduce a substantial time difference between an end point of a first scan mode activation period of the input latching logic and between a start point of a second scan mode activation period of the output latching logic.

Abstract: A method and device for testing an integrated circuit. The method includes selecting between a shadow latch data retention mode and a shadow latch test mode; performing first test of an integrated circuit; storing, at the shadow latch if the shadow latch test mode is selected, information representative of a first test-imposed state; performing a second test of the integrated circuit; and generating a test equipment detectable signal if the first test-imposed state differs from a second test-imposed state of the tested latch.

Abstract: A device and method for power management. The method includes receiving an indication about a load of a circuit, determining at least one long-term activation parameter in view of a circuit load pattern during at least one long period; determining at least one short-term activation parameter in response to an expected short period load change of the circuit; and providing least one clock signal and at least one supply voltage in response to the long-term activation parameter and in response to the short-term supply parameter.

Abstract: A method and device for managing metastable signals. The device includes: a first latch and a second latch, a multiple switching point circuit, connected between an output node of the first latch and an input node of the second latch, wherein the multiple switching point circuit includes at least one pull up transistor and at least one pull down transistor that are selectively activated in response to a feedback signal provided from the second latch and in response to a an output signal of the first latch such as to define at least a low switching point that is lower than a high switching point of the multiple-switching point circuit; wherein a switching point of an inverter within the first latch is between the high and low switching points.

Abstract: A method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; characterized by defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle. A device having frame synchronization capabilities, the device includes a clock signal provider and at least one component connected to a data line. The clock signal provider is adapted to provide a high frequency clock signal over a clock line during a transmission of information over the data line.

Abstract: A method for determining system and software configuration that includes: calculating a power consumption estimate of a modeled system associated with an execution of a certain software code; and altering, in response to the power consumption estimate, the certain software code or the modeled system. A method of determining a power consumption of a system that executed a software code, the method includes the stages of: providing a reduced instruction set representation of the software code; and calculating a power consumption estimate of a modeled system associated with an execution of the reduced instruction set representation of the software code.

Abstract: A system having voltage level shifting capabilities, the system includes a logic circuit and a multiple level voltage supply circuit; wherein the logic circuit comprises at least one PMOS transistor and at least one NMOS transistor; wherein the logic circuit receives an input signal, receives a voltage supply signal from the multiple level voltage supply circuit, and outputs an output signal via a first node; wherein the input signal has a low voltage swing between a low level supply voltage and a rail voltage; wherein the output signal has a high voltage swing between a high level supply voltage and the rail voltage; and wherein the multiple level voltage supply circuit selects, in response to a level of the output signal, whether to provide to the supply node of the logic circuit a high level supply voltage or a low level supply voltage.

Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system. The apparatus includes a hardware module, adapted to receive at least one indication of a load of the system and to determine a voltage level and a clock signal frequency to be provided to the system, and a software module, adapted to configure a voltage source and a clock signal source in response to the determination. The method includes: (i) receiving, at a hardware module, indication of a load of a system; (ii) determining, by the hardware module, a voltage level and a clock signal frequency to be provided to the system; and (iii) configuring, by a software module, a voltage source and a clock signal source in response to the determination.

Abstract: An integrated circuit and a method for testing an integrated circuit.