Abstract: An integrated circuit device comprises a signal processing system having at least one first signal processing module fabricated by way of a first production process; and at least one second signal processing module fabricated by way of a second production process, wherein the second production process is different to the first production process. The signal processing system further comprises a signal processing management module arranged to: determine a desired system performance of the integrated circuit device; determine at least one operating condition of the signal processing system; and configure a signal processing operating mode of the signal processing system based at least partly on: the determined desired system performance; the at least one determined operating condition; and at least one of the first production process and the second production process.

Abstract: A secure real time clock (RTC) system is provided, comprising a secure RTC, a frequency signal generator, and a frequency adjuster connected between the secure RTC and the frequency signal generator to receive a signal having a first frequency from the frequency signal generator. On receipt of a first control signal the frequency adjuster outputs the signal having the first frequency to the secure RTC, and on receipt of a second control signal the frequency adjuster adjusts the signal having the first frequency to generate a signal having a second frequency, the second frequency being lower than the first frequency, and outputs the signal having the second frequency to the secure RTC.

Abstract: An integrated circuit comprises clock gating circuitry comprising at least one gating component located within a clock distribution network and arranged to enable at least one part of the clock distribution network to be gated, and gating control circuitry arranged to cause the at least one gating component to disable the at least one part of the clock distribution network upon certain conditions being fulfilled. The clock gating circuitry further comprises clock gating disabling circuitry configurable to enable the gating of the at least one part of the clock distribution network to be disabled.

Abstract: An integrated circuit comprises reference voltage generation circuitry for providing a reference voltage for use within a transmission of electrical signals. The reference voltage generation circuitry comprises a reference voltage node operably coupled via a plurality of resistance elements to a plurality of signal nodes such that the reference voltage node assumes as the reference voltage an average of the voltage values of the signal nodes to which it is coupled.

Abstract: A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.

Abstract: A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states, determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.

Abstract: An integrated circuit and a method. The integrated circuit includes an internal component having an output for providing a driven input signal; an output driver, connected to the internal component, for converting said driven input signal in an output signal; an output pad for outputting said output signal to a component outside the integrated circuit; a power grid configured to supply a supply voltage to the output driver; a controllable current consuming component connected to the power grid, said connectable current consuming component being controllable to consume current in accordance with a supply voltage change reduction pattern; a change detector connected to the internal component and the controllable current consuming component, for detecting a change in said driven input signal prior to said change resulting in a change in said output signal and to control said current consuming component to consume current in response to said detecting.

Abstract: A multiple instruction execution modules device that comprises a first instruction execution module and a second instruction execution module and a context switch controller; wherein the first instruction execution module is logically identical to the second instruction execution module but substantially differs from the second instruction execution module by at least one power consumption characteristic; wherein the context switch controller controls a context switch between the first instruction execution module and the second instruction execution module; wherein an instruction execution module that its context has been transferred is shut down.

Abstract: A device that has failure recovery capabilities and a method for power recovery. The method includes: detecting a potential power failure in response to a decrement rate of a supply voltage, and applying at least one failure recovery measure in response to a detected potential power failure. The device includes: a power source, an energy reservoir, at least one component, and a power failure circuit, adapted to detect a potential power failure in response to a decrement rate of a supply voltage.

Abstract: An electronic device comprises a first component susceptible to a wearout effect, operation of which first component depends on an operating parameter, and a second component having an on-state and an off-state. The electronic device further comprises a time estimator for updating an estimate of an accumulated time the second component was in the on-state; and a controller for controlling the operating parameter on the basis of the accumulated time estimate so as to respond to the expected wearout effect. The first component and the second component may be the same, or the first component may have an on-state correlated to the on-state of the second component. The operating parameter may, for example, be a level or amplitude or correction value of one of the following: a voltage applied at the first component, an electric current fed to the first component, and a power provided to the first component. A method of operating such an electronic device is also disclosed.

Abstract: A device having a power supply monitoring capabilities, the device includes: a power supply unit; at least one real time clock generator counter adapted to receive a supply voltage from the power supply unit; a fixed value storage circuit that is un-accessible to software executed by a processor; wherein the fixed value storage circuit stores a fixed value; wherein the fixed value includes multiple bits; a volatile storage unit, being accessible to the processor; wherein the volatile storage unit is adapted to: (i) store a reset value after being reset; (ii) receive the fixed value during an initialization state; and (iii) store the fixed value until being reset; wherein the volatile storage unit is designed such that there is a low probability that the reset value equals the fixed value; and a comparator adapted to provide a tamper indication if the fixed value stored at the fixed value storage circuit differs from a value stored at the volatile storage unit.

Abstract: A device and a method for estimating a current; the method includes: setting an impedance of a power gating circuit to a measurement value; wherein the power gating circuit selectively provides power to a circuit of an integrated circuit; measuring, during a measurement period, an electrical parameter indicative of a current that flows through the power gating circuit; and reducing an impedance of the power gating circuit to a power provision value to reduce a voltage developed on the power gating circuit during a power provision period.

Abstract: A device and a method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle.

Abstract: A system that includes a first circuitry, a second circuitry, a first supply unit and a second supply unit; characterized by including a second control unit adapted to determine a level of a second supply voltage supplied by the second supply unit in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages. A method for controlling voltage level and clock signal frequency supplied to a system, the method includes providing a first supply voltage to a first circuitry and providing a second supply voltage to a second circuitry; characterized by determining a level of the second supply voltage in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages.

Abstract: A method for controlling power consumption of a processor, the method includes: receiving an indicator that indicates that the processor is expected to change its activity; determining, in response to the indicator and to a current power consumption of the processor, whether to change a frequency of a clock signal that is provided to the processor; and changing, if determining to change the frequency of the clock signal, the frequency of the clock signal by a reduction of the frequency of the clock signal that is followed by an increment of the frequency of the clock signal; wherein the changing of the frequency of the clock signal is responsive to an expected change of a supply voltage that is supplied to the processor as a result of a possible change in a power consumption of the processor due to an expected change of activity of the processor.

Abstract: A method and an electronic circuit, the electronic circuit includes: a first circuit; a leakage measurement circuit arranged to determine a leakage level of the first circuit when the first circuit is in a standby mode, and to determine an information maintenance level of a supply voltage in response to the leakage level; and a voltage supply circuit arranged to provide to the first circuit a supply voltage of a functional level when the first circuit is in a functional mode, and to provide to the first circuit a supply voltage of the information maintenance level when the first circuit is in the standby mode; wherein the first circuit is arranged to maintain information when provided with the supply voltage of the information maintenance level.

Abstract: A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module; and providing a secured real time clock signal when the multiple input ports of the secured real time clock module are locked and when the multiple input ports of the secured real time clock module are unlocked; wherein changes in a supply voltage results in a supply voltage induced changes of an input signal provided to an input port of the secured real time clock module; wherein a maximal frequency of the supply voltage induced changes of the input signal is lower than the high frequency of the predefined high frequency code.

Abstract: A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests.

Abstract: A device and method for power management. The method includes receiving an indication about a load of a circuit, determining at least one long-term activation parameter in view of a circuit load pattern during at least one long period; determining at least one short-term activation parameter in response to an expected short period load change of the circuit; and providing least one clock signal and at least one supply voltage in response to the long-term activation parameter and in response to the short-term supply parameter.

Abstract: A method and an electronic circuit, the electronic circuit includes: a module that comprises multiple flip-flops and a control signal providing circuit; a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops; wherein the each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transisto