Abstract: A system, that includes: a memory unit adapted to store state duration statistics indicative of possible low power state durations and probabilities associates with the possible state durations; and a power controller, adapted to: receive a request to cause a circuit to enter a next state, and assist in causing the circuit to enter the next state if during a delay period that follows a reception of the request the power controller does not receive a request to cause the circuit to exit the next state; wherein the delay period is determined in response to: (i) the next state duration statistics, (ii) power saving gained from entering the next state; and (iii) power penalty associated with entering the next state and exiting the next state.

Abstract: A method for reducing power consumption, and a system having power reduction capabilities, the method includes: storing, at a first circuit, data representative of a state of a second circuit, entering a low power mode, exiting low power mode, providing a default data value to the second circuit after exiting from the low power mode, and selectively providing data from the first circuit to the second circuit in response to the value of data and to a characteristic of a third circuit coupled to the first and second circuits.

Abstract: A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events, in response to the possible timing of signals; and determining hold parameters in response to the relationships. A computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to define at least one internal delay of a designed component, characterized by causing the processor to define a cell that is characterized by multiple hold times and multiple setup values for a certain clock skew value.

Abstract: A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value.

Abstract: A method and a device for estimating parameter variations of transistors that belong to the same circuit. The method includes: providing the first circuit; providing a test circuit adapted to perform a first function and a stacked test circuit adapted to perform a second function that substantially equals the first function; wherein the test circuit, the stacked test circuit and the first circuit are processed under substantially the same processing conditions; determining a relationship between a parameter of the test circuit and a parameter of the stacked test circuit; and estimating parameter variations of transistors that belong to the first circuit in response to the determined relationship.

Abstract: A device that includes: (i) an evaluated circuit; (ii) a leakage current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a leakage current of the evaluated circuit; (iii) a switching current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a switching induced current of the evaluated circuit; (iv) a power reduction module that is configured to: (a) compare between an oscillation frequency of the leakage current dependent oscillator and an oscillation frequency of the switching current dependent oscillator, to provide a current comparison result; (b) select a power reduction technique out of a dynamic voltage and frequency scaling technique and a power gating technique in view of the current comparison result; and (c) apply the selected power reduction technique.

Abstract: A method and device for testing an integrated circuit. The method includes selecting between a shadow latch data retention mode and a shadow latch test mode; performing a first test of an integrated circuit; storing, at the shadow latch if the shadow latch test mode is selected, information representative of a first test-imposed state; performing a second test of the integrated circuit; and generating a test equipment detectable signal if the first test-imposed state differs from a second test-imposed state of the tested latch.

Abstract: A method and apparatus for reducing power consumption of transistor-based circuit is disclosed. The method includes receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit. The apparatus is adapted to receive a low power mode indication, and includes: a determining circuit to determine whether to supply power to at least a portion of the transistor-based circuit in response a state of the transistor-based circuit prior the receiving of the low power mode indication; and a power gating, adapted to selectively provide power to at least a portion of the transistor-based circuit in response to the determination.

Abstract: A method for power reduction, the method includes determining whether to power down the at least portion of the component in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power mode, and selectively providing power to at least a portion of a component of an integrated circuit during a low power mode. A device having power reduction capabilities, the device includes power switching circuitry, and a power management circuitry adapted to determine whether to power down at least the portion of the component during a low power mode in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power.

Abstract: A method for testing an integrated circuit, that includes: (a) providing a first signal to a first path that starts within the integrated circuit and ends at a first memory element that is followed by a first IO pad, and providing a second signal to a second path that starts within the integrated circuit and ends at a second memory element that is followed by a second IO pad; (b) comparing between a first test result and a second test result, wherein the first test result represents a state of the first memory element sampled a predefined period after a provision of the first signal and the second test result represents a state of the second memory element sampled a predefined period after a provision of the second signal; (c) altering the predefined period; and (d) repeating the stages of providing, comparing and altering until detecting a time difference between a first path propagation period and a second path propagation period.

Abstract: A system that includes at least one component adapted to execute at least one application, characterized by including a controller adapted to receive at least one load indication of at least one component of the system and to selectively alter at least one control parameter of a voltage and clock frequency management scheme; whereas the system is adapted to apply the voltage and clock frequency management scheme. A method for controlling voltage level and clock frequency supplied to a system, the method includes receiving at least one load indication of at least one component of the system; characterized repeating the stages of: selectively altering at least one control parameter of a voltage and clock frequency management scheme; and applying the voltage and clock frequency management scheme.

Abstract: An integrated circuit comprising oscillator circuitry is arranged to generate a clock signal for functional logic module of the integrated circuit. The oscillator circuitry comprises a plurality of propagation paths, and is arranged to apply a transition signal to inputs of the plurality of propagation paths, and to cause the output clock signal to transition based on a propagation of the transition signal through a determined set of the propagation paths.

Abstract: A system for providing an output clock signal, the system includes: (a) a first clock divider, adapted to receive an input clock signal and to provide a first divider output clock signal having a frequency that is lower than a frequency of the input clock signal; and (b) a second clock divider, adapted to select a second divider input clock signal out of the input clock signal and the first divider output clock signal, and to provide the output clock signal having a frequency that is lower than the frequency of the second divider input clock signal.

Abstract: A method and a device having synchronizing capabilities, the device includes; (i) a first circuit that is adapted to receive a first clock signal; (ii) a second circuit that is adapted to receive a second clock signal; wherein the first and second clock signals and mutually asynchronous; and a (iii) synchronizer that is coupled between the first and second circuit and is adapted to receive the second clock signal, to receive an input signal from the first circuit and to output an output signal of definite values to the second circuit, wherein the input signal is synchronized with the first clock signal and the output signal is synchronized with the second clock signal.

Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system. The apparatus includes a hardware module, adapted to receive at least one indication of a load of the system and to determine a voltage level and a clock signal frequency to be provided to the system, and a software module, adapted to configure a voltage source and a clock signal source in response to the determination. The method includes: (i) receiving, at a hardware module, indication of a load of a system; (ii) determining, by the hardware module, a voltage level and a clock signal frequency to be provided to the system; and (iii) configuring, by a software module, a voltage source and a clock signal source in response to the determination.

Abstract: A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing logic is further arranged to output a gated clock signal substantially corresponding to the selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state. The clock gating logic further comprises polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of a comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic.

Abstract: A device that includes an error detection circuit that is configured to detect a timing error resulting from a fast voltage drop by comparing a signal from a critical path to a signal from a replica path; and a clock signal provider that is adapted to receive a clock signal and to delay, by a fraction of the clock cycle and in response to a detection of the timing error, the clock signal to provide a delayed clock signal that is provided to a clocked circuit that is coupled to the critical path; and a controller that is configured determine a level of a supply voltage in response to a capability of the error detection circuit and the clock signal provider to manage fast voltage drops; wherein the supply voltage is provided to at least one component of the critical path.

Abstract: A method and device for managing metastable signals. The device includes: a first latch and a second latch, a multiple switching point circuit, connected between an output node of the first latch and an input node of the second latch, wherein the multiple switching point circuit includes at least one pull up transistor and at least one pull down transistor that are selectively activated in response to a feedback signal provided from the second latch and in response to a an output signal of the first latch such as to define at least a low switching point that is lower than a high switching point of the multiple-switching point circuit; wherein a switching point of an inverter within the first latch is between the high and low switching points.

Abstract: A system that includes a first flip flop that is serially coupled to a second flip flop. The first flip flop includes a transfer circuit that is coupled between a master latch and a slave latch. The master latch of the first flip flop latches a scan data signal during a first portion of a cycle of a first clock signal that is provided to the first flip flop. The transfer circuit is conductive during a sub-portion of a second portion of the cycle of the first clock signal. The sub-portion starts after an occurrence of a predefined change in a control signal provided to the slave latch. The predefined change occurs after an estimated start of a first portion of a cycle of a second clock signal that is provided to the second flip flop. A master latch of the second flip flop latches the scan data signal during a first portion of a next cycle of the second clock signal.

Abstract: A method for sharing charge between IO circuits, the method includes providing an integrated circuit that comprises multiple IO circuits, each comprising an IO pad. The method is characterized by including: determining to share a charge between multiple IO circuits; and sharing charge between the multiple IO circuits by coupling the multiple IO circuits to a shared circuit that is characterized by a state that reflects multiple iterations of sharing charge operations.