Abstract: A system that includes at least one component adapted to execute at least one application, characterized by including a controller adapted to receive at least one load indication of at least one component of the system and to selectively alter at least one control parameter of a voltage and clock frequency management scheme; whereas the system is adapted to apply the voltage and clock frequency management scheme. A method for controlling voltage level and clock frequency supplied to a system, the method includes receiving at least one load indication of at least one component of the system; characterized repeating the stages of: selectively altering at least one control parameter of a voltage and clock frequency management scheme; and applying the voltage and clock frequency management scheme.

Abstract: A device that has failure recovery capabilities and a method for power recovery. The method includes: detecting a potential power failure in response to a decrement rate of a supply voltage, and applying at least one failure recovery measure in response to a detected potential power failure. The device includes: a power source, an energy reservoir, at least one component, and a power failure circuit, adapted to detect a potential power failure in response to a decrement rate of a supply voltage.

Abstract: A device for regulating a voltage supply to a semiconductor device, the device comprising memory for storing a plurality of performance ranges, wherein the respective performance ranges are associated with a respective supply voltage; means for measuring the performance of the semiconductor device; and a regulator for modifying the supply voltage to the semiconductor device if the measured performance of the semiconductor device is not within a predetermined portion of the performance range associated with the voltage supplied to the semiconductor device.

Abstract: A method and a device for estimating parameter variations of transistors that belong to the same circuit. The method includes: providing the first circuit; providing a test circuit adapted to perform a first function and a stacked test circuit adapted to perform a second function that substantially equals the first function; wherein the test circuit, the stacked test circuit and the first circuit are processed under substantially the same processing conditions; determining a relationship between a parameter of the test circuit and a parameter of the stacked test circuit; and estimating parameter variations of transistors that belong to the first circuit in response to the determined relationship.

Abstract: A method for reducing power consumption of transistor-based circuit, the method includes: of receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit.

Abstract: A method for media access control, the method includes generating at least one media access grant in response to at least one media access request. The method is characterized by monitoring a data line, while maintaining at least a clock line in a low power mode, to detect at least one media access request generated by at least one component connected to the data line and to the clock line; and forcing the at least clock line to exit the low power mode and starting a contention prevention period, when the media access controller or at least one component requests to access the data line. A device including multiple components that are connected to a data line, and adapted to transmit information over the data line at a transmission rate responsive to a first clock rate.

Abstract: A method for synchronizing a transmission of information over a bus, and a device having synchronization capabilities.

Abstract: A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value.

Abstract: A method for configuring IO pads, the method includes determining a current configuration of multiple IO pads of an integrated circuit and whereas the method is characterized by generating multiple boundary scan register words that comprise Configuration information; and repeating the stage of serially writing a certain boundary scan register word to a boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits. A device that includes a core, connected to a boundary scan register, a TAP controller and multiple IO pad circuits, the device is characterized by including a control circuit adapted to determine a current configuration of the IO pads, to generate multiple boundary scan register words that comprise configuration information; and to control a repetition of: writing a certain boundary scan register word to the boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits.

Abstract: A system that includes a first circuitry, a second circuitry, a first supply unit and a second supply unit; characterized by including a second control unit adapted to determine a level of a second supply voltage supplied by the second supply unit in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages. A method for controlling voltage level and clock signal frequency supplied to a system, the method includes providing a first supply voltage to a first circuitry and providing a second supply voltage to a second circuitry; characterized by determining a level of the second supply voltage in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages.

Abstract: A high-speed voltage regulating apparatus and a method for high-speed voltage regulation. The apparatus includes: (A) a regulator, adapted to provide a regulated voltage; (B) switching circuitry, connected to the regulator, adapted to either (i) connect the regulator to an output node or (ii) disconnect the regulator from the output node; whereas the output node is connected to a dynamic power consuming device and to a load capacitor; (C) control logic, connected to the regulator, adapted to receive at least an indication reflecting a voltage of the output node and to control the switching circuitry such that the regulator is disconnected from the output node to facilitate a decrease in the voltage of the output node.

Abstract: A method for storing state information, the method includes storing, at a first circuit, state information representative of a state of a second circuit while the second circuit enters a low power mode; characterized by receiving an indication that a task switching from a first task to a second task should occur; storing a state information representative of a state of the second circuit, at the first circuit; receiving an indication that the first task should be resumed; and writing the stored state information from the first circuit to the second circuit. A system includes a first circuit and a second circuit, whereas the first circuit is connected to the second circuit and is adapted to store state information representative of a state of a second circuit; characterized by including a controller adapted to control a storage of the state information if at least a portion of the second circuit is powered down or if the second circuit is associated with a task switching operation.

Abstract: A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events, in response to the possible timing of signals; and determining hold parameters in response to the relationships. A computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to define at least one internal delay of a designed component, characterized by causing the processor to define a cell that is characterized by multiple hold times and multiple setup values for a certain clock skew value.

Abstract: A method for power reduction, the method includes determining whether to power down the at least portion of the component in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power mode, and selectively providing power to at least a portion of a component of an integrated circuit during a low power mode. A device having power reduction capabilities, the device includes power switching circuitry adapted to selectively provide power to at least a portion of a component of the device during a low power mode, and a power management circuitry adapted to determine whether to power down at least the portion of the component during a low power mode in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power.

Abstract: A method for reducing power consumption, and a system having power reduction capabilities, the method includes: storing, at a first circuit, data representative of a state of a second circuit, entering a low power mode, exiting low power mode, providing a default data value to the second circuit after exiting from the low power mode, and selectively providing data from the first circuit to the second circuit in response to the value of data and to a characteristic of a third circuit coupled to the first and second circuits. The system includes: a first circuit, a second circuit and a third circuit. The third circuit is connected between the first circuit and the second circuit. The first circuit is adapted to store data representative of a state of the second circuit. The first circuit is activated during a low power mode while the second circuit is deactivated during the low power mode. The second circuit is adapted to enter a default state after exiting from the low power mode.

Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system.

Abstract: Biasing a transistor connected to a voltage converter, the method includes: (i) providing at least one bias voltage to at least one well of at least one transistor of a test circuitry; (ii) measuring at least one parameter of a test circuitry representative of at least one characteristic of the transistor and of at least one characteristic of the voltage converter; (iii) altering at least one bias voltage and repeating the stages of providing and measuring until a predefined control criteria is fulfilled; and (iv) providing a voltage bias to a well of the transistor in response to the measurements.

Abstract: A high-speed voltage regulating apparatus and a method for high-speed voltage regulation. The apparatus includes: (A) a regulator, adapted to provide a regulated voltage; (B) switching circuitry, connected to the regulator, adapted to either (i) connect the regulator to an output node or (ii) disconnect the regulator from the output node; whereas the output node is connected to a dynamic power consuming device and to a load capacitor; (C) control logic, connected to the regulator, adapted to receive at least an indication reflecting a voltage of the output node and to control the switching circuitry such that the regulator is disconnected from the output node to facilitate a decrease in the voltage of the output node.

Abstract: A device and a method for biasing a transistor connected to a voltage converter, the method includes: (i) providing at least one bias voltage to at least one well of at least one transistor of a test circuitry; (ii) measuring at least one parameter of a test circuitry representative of at least one characteristic of the transistor and of at least one characteristic of the voltage converter; (iii) altering at least one bias voltage and repeating the stages of providing and measuring until a predefined control criteria is fulfilled; and (iv) providing a voltage bias to a well of the transistor in response to the measurements.

Abstract: An apparatus for voltage level shifting comprising a voltage shifter for converting a first input voltage to a second output voltage; a first semiconductor switch arrangement and a second semiconductor switch arrangement that are responsive to a control signal for switching the voltage shifter between a first operational state and a second operational state and thereby allow the voltage shifter to be placed in the first operational state when the first input voltage is within a first voltage region and to place the voltage shifter in the second operational state when the first input voltage is in a second voltage region.