Patents by Inventor Michael RIZZOLO

Michael RIZZOLO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SELECTIVE ILD DEPOSITION FOR FULLY ALIGNED VIA WITH AIRGAP
    Publication number: 20190267278
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 29, 2019
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • LOCATION-SPECIFIC LASER ANNEALING TO IMPROVE INTERCONNECT MICROSTRUCTURE
    Publication number: 20190262941
    Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Benjamin David BRIGGS, Lawrence A. CLEVENGER, Bartle H. DEPROSPO, Michael RIZZOLO
  • Fully aligned via employing selective metal deposition
    Patent number: 10395986
    Abstract: A method is presented for creating a fully-aligned via (FAV) by employing selective metal deposition. The method includes forming metal lines within a first inter-layer dielectric (ILD) layer, forming a second ILD layer over the first ILD layer, forming a lithographic stack over the second ILD layer to define areas where via growth is prevented, recessing the lithographic stack to expose a top surface of the metal lines where via growth is permitted by the lithographic stack, and performing metal growth over the exposed top surface of the metal lines where via growth is permitted.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, James J. Kelly, Donald F. Canaperi, Michael Rizzolo, Lawrence A. Clevenger
  • Self aligned via and pillar cut for at least a self aligned double pitch
    Patent number: 10395977
    Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Terry A. Spooner, Theodorus E. Standaert
  • Multi-angled deposition and masking for custom spacer trim and selected spacer removal
    Patent number: 10388525
    Abstract: Multi-angled deposition and masking techniques are provided to enable custom trimming and selective removal of spacers that are used for patterning features at sub-lithographic dimensions. For example, a method includes forming a sacrificial mandrel on a substrate, and forming first and second spacers on opposing sidewalls of the sacrificial mandrel. The first and second spacers are formed with an initial thickness Ts. A first angle deposition process is performed to deposit a material (e.g., insulating material or metallic material) at a first deposition angle A1 to form a first trim mask layer on an upper portion of the first spacer and the sacrificial mandrel while preventing the material from being deposited on the second spacer. A spacer etch process is performed to trim the first spacer to a first thickness T1, which is less than Ts, using the first trim mask layer as an etch mask.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Sean D. Burns, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Resistive memory crossbar array compatible with Cu metallization
    Patent number: 10381563
    Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Michael Rizzolo, Lawrence A. Clevenger, Shyng-Tsong Chen
  • METHOD AND STRUCTURE TO CONSTRUCT CYLINDRICAL INTERCONNECTS TO REDUCE RESISTANCE
    Publication number: 20190237402
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.
    Type: Application
    Filed: January 29, 2018
    Publication date: August 1, 2019
    Inventors: Benjamin D. Briggs, Michael Rizzolo, Christopher J. Penny, Huai Huang, Lawrence A. Clevenger, Hosadurga Shobha
  • Location-specific laser annealing to improve interconnect microstructure
    Patent number: 10366920
    Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Michael Rizzolo
  • Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device
    Patent number: 10366952
    Abstract: A method of forming a semiconductor device includes forming a porous dielectric layer including a recessed portion, forming a conductive layer in the recessed portion of the porous dielectric layer, and forming a conformal cap layer on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Method of manufacturing self-aligned interconnects by deposition of a non-conformal air-gap forming layer having an undulated upper surface
    Patent number: 10361157
    Abstract: A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths; and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Selective ILD deposition for fully aligned via with airgap
    Patent number: 10361117
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Multi-angled deposition and masking for custom spacer trim and selected spacer removal
    Patent number: 10361079
    Abstract: Multi-angled deposition and masking techniques are provided to enable custom trimming and selective removal of spacers that are used for patterning features at sub-lithographic dimensions. For example, a method includes forming a sacrificial mandrel on a substrate, and forming first and second spacers on opposing sidewalls of the sacrificial mandrel. The first and second spacers are formed with an initial thickness TS. A first angle deposition process is performed to deposit a material (e.g., insulating material or metallic material) at a first deposition angle A1 to form a first trim mask layer on an upper portion of the first spacer and the sacrificial mandrel while preventing the material from being deposited on the second spacer. A spacer etch process is performed to trim the first spacer to a first thickness T1, which is less than TS, using the first trim mask layer as an etch mask.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Sean D. Burns, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Co-fabrication of magnetic device structures with electrical interconnects having reduced resistance through increased conductor grain size
    Patent number: 10361364
    Abstract: A method of forming magnetic device structures and electrical contacts, including removing a portion of a second interlayer dielectric (ILD) layer to expose an underlying portion of a cap layer in a first device region, wherein the cap layer is on a first ILD layer, while leaving an ILD block in a second device region, forming a spacer layer on the exposed portion of the cap layer in the first device region, forming an electrical contact layer on the spacer layer in the first device region, forming a magnetic device layer on the electrical contact layer and ILD block, removing portions of the magnetic device layer to form a magnetic device stack on the ILD block, and removing portions of the electrical contact layer to form electrical contact pillars, wherein the portions of the electrical contact layer and portions of the magnetic device layer are removed at the same time.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Liying Jiang, Sebastian Naczas, Michael Rizzolo, Chih-Chao Yang
  • AUTO-INCORRECT IN CHATBOT HUMAN-MACHINE INTERFACES
    Publication number: 20190215282
    Abstract: Context appropriate errors are injected into conversational text generated by conversational agents. The conversational agent creates an imperfect conversational text containing at least one text entry error added to the original conversational text. A confidence level that at least one of context and meaning of the imperfect conversational text is consistent with the context and meaning of the original conversational text is determined, and the imperfect conversational text is communicated to a human recipient if the confidence level is above a pre-defined threshold.
    Type: Application
    Filed: January 9, 2018
    Publication date: July 11, 2019
    Inventors: Benjamin D. BRIGGS, Lawrence A. CLEVENGER, Leigh Anne H. CLEVENGER, Christoper J. PENNY, Michael RIZZOLO, Aldis SIPOLINS
  • Selective deposition and nitridization of bottom electrode metal for MRAM applications
    Patent number: 10347825
    Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, and etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches. The method further includes selectively depositing an electrode over the top surface of the exposed metal and nitridizing the electrode to form a diffusion barrier between chip components and the metal.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Joe Lee, Christopher J. Penny, Michael Rizzolo, Chih-Chao Yang
  • STRUCTURE, SYSTEM, METHOD, AND RECORDING MEDIUM OF IMPLEMENTING A DIRECTED SELF-ASSEMBLED SECURITY PATTERN
    Publication number: 20190193452
    Abstract: A document including a Directed Self-Assembly (DSA) pattern including a unique and randomized pattern embedded on the document, where the DSA is formed by using two different-length polymer chains.
    Type: Application
    Filed: February 27, 2019
    Publication date: June 27, 2019
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Barlet H. DeProspo, Michael Rizzolo
  • EXTREME ULTRAVIOLET (EUV) LITHOGRAPHY PATTERNING METHODS UTILIZING EUV RESIST HARDENING
    Publication number: 20190198325
    Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement a surface-hardened EUV resist mask to pattern features in multiple layers. A layer of EUV resist material is formed on a substrate. An EUV resist mask is formed by exposing and developing the layer of EUV resist material. A surface-hardened EUV resist mask is formed by applying a surface treatment to an upper surface of the EUV resist mask to form an etch-resistant layer that is embedded in the upper surface of the EUV resist mask. At least one layer of the substrate is patterned using the surface-hardened EUV resist mask. The surface treatment can be implemented using a neutral atom beam (NAB) process which is configured to implant a chemical or metallic species into the upper surface of the EUV resist mask to form the etch-resistant layer.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Inventors: Benjamin D. Briggs, Michael Rizzolo, Ekmini Anuja De Silva, Chih-Chao Yang, Lawrence A. Clevenger
  • BACK END OF LINE ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATION
    Publication number: 20190181091
    Abstract: Techniques facilitating back end of line electrical fuse structure and method of fabrication are provided. A device can comprise a first metal interconnect formed in a dielectric layer of a semiconductor chip. The device can also comprise a second metal interconnect formed in the dielectric layer and adjacent to the first metal interconnect. Further, the device can comprise a vertical electrical fuse element comprising a first portion of a conductive material deposited on a first surface of the first metal interconnect and a second portion of the conductive material deposited on a second surface of the second metal interconnect. The vertical electrical fuse element can comprise a first region comprising a first thickness and a second region comprising a second thickness different than the first thickness.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • SELECTIVE ILD DEPOSITION FOR FULLY ALIGNED VIA WITH AIRGAP
    Publication number: 20190181033
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 13, 2019
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Integrated magnetic tunnel junction (MTJ) in back end of line (BEOL) interconnects
    Patent number: 10319783
    Abstract: A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Michael Rizzolo, Theodorus E. Standaert