Abstract: An anti-counterfeiting method, system, and non-transitory computer readable medium including a transfer circuit configured to transfer a Directed Self-Assembly (DSA) pattern including a unique and randomized pattern onto a strip, an embedding circuit configured to embed the strip on a document, and a verification circuit configured to verify that the unique and randomized pattern embedded on the document corresponds to the document.

Abstract: A semiconductor interconnect structure and a method of fabricating the same are provided. The semiconductor interconnect structure includes a sea of interconnect lines including metal lines and neighboring dummy lines. The semiconductor interconnect structure further includes a dielectric layer arranged between the sea of lines.

Abstract: Tooling apparatus and methods are provided to fabricate semiconductor devices in which controlled thermal annealing techniques are utilized to modulate microstructures of metallic interconnect structures. For example, an apparatus includes a single platform semiconductor processing chamber having first and second sub-chambers. The first sub-chamber is configured to receive a semiconductor substrate comprising a metallization layer formed on a dielectric layer, wherein a portion of the metallization layer is disposed within an opening etched in the dielectric layer, and to form a stress control layer on the metallization layer. The second sub-chamber comprises a programmable hot plate which is configured to perform a thermal anneal process to modulate a microstructure of the metallization layer while the stress control layer is disposed on the metallization layer, and without an air break between the process modules of forming the stress control layer and performing the thermal anneal process.

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, and etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches. The method further includes selectively depositing an electrode over the top surface of the exposed metal and nitridizing the electrode to form a diffusion barrier between chip components and the metal.

Abstract: A magnetic random access memory (MRAM) device includes a conductor disposed in an insulating material of a lower wiring layer, a magnetic tunnel junction (MTJ) structure formed in an upper wiring layer, and a landing pad formed in an intermediary wiring layer between the lower and upper wiring layers, the landing pad extending from a top surface of the conductor to a height above the intermediary wiring layer, wherein the landing pad connects the MJT structure to the conductor.

Abstract: The present invention may receive a plurality of unlock instructions based on determining a location is secured from access by the drone. The present invention may use the plurality of received unlock instructions to access the location with an access device while determining the drone is present at the drop off location. The present invention may use the plurality of received unlock instructions to re-secure the location with the access device when determining successful delivery of a package by the drone, and may monitor a security of the location.

Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.

Abstract: A computer-mediated physical damping feedback system includes a motion damping device, a voltage conversion controller, and a voltage generator controller. The motion damping device is worn by a participant present in a real-world environment, and is configured to vary a moveable flexibility of the participant in response to receiving an electrical voltage. The voltage conversion controller is in signal communication with a computer-mediated environment engine (CMEE) controller, and is configured to determine a voltage level of the electrical voltage based at least in part on the interaction between the participant and a computer-mediated environment. The voltage generator controller is in signal communication with the motion damping device and the voltage conversion controller. The voltage generator controller is configured to generate the electrical voltage at the voltage level that induces the stress applied by the motion damping device.

Abstract: A method is presented for forming a semiconductor device. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form a plurality of trenches for receiving a first conducting material, forming a resistive switching memory element over at least one trench of the plurality of trenches, the resistive switching memory element having a conducting cap formed thereon, and depositing a dielectric cap over the trenches. The method further includes etching portions of the insulating layer to expose a section of the dielectric cap formed over the resistive switching memory element, etching the exposed section of the dielectric cap to expose the conducting cap of the resistive switching memory element, and forming a barrier layer in direct contact with the exposed section of the conducting cap.

Abstract: A method is presented for forming a semiconductor device. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form a plurality of trenches for receiving a first conducting material, forming a resistive switching memory element over at least one trench of the plurality of trenches, the resistive switching memory element having a conducting cap formed thereon, and depositing a dielectric cap over the trenches. The method further includes etching portions of the insulating layer to expose a section of the dielectric cap formed over the resistive switching memory element, etching the exposed section of the dielectric cap to expose the conducting cap of the resistive switching memory element, and forming a barrier layer in direct contact with the exposed section of the conducting cap.

Abstract: Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.

Abstract: A semiconductor structure includes a dielectric layer having a trench formed therein and a barrier layer formed on a bottom and sidewalls of the trench, and on a top surface of the dielectric layer. The trench comprises a flared top gap opening and additional area at the bottom such that the top and bottom of the trench are wider than sidewalls of the trench. A thickness of the barrier layer on the bottom of the trench and on the top surface of the dielectric layer is controlled using one or more cycles comprising forming an oxidized layer using a neutral beam oxidation and removing the oxidized layer using an etching process, such that the thickness of the barrier layer on the bottom of the trench and on the top surface of the dielectric layer is substantially the same as the thickness of the barrier layer on sidewalls of the trench.

Abstract: Techniques for motivating a user during a workout using different coaching styles are provided. In one aspect, a method for motivational coaching of a user during workout sessions includes the steps of: selecting a coaching style for the user based on input from the user and from coaching styles used for at least one other user; determining, during a workout session, whether the coaching style should be changed to enhance performance of the user based on data obtained from the user via a mobile device worn by the user; changing the coaching style if it is determined that the coaching style should be changed to enhance performance of the user; continuing with a current coaching style if it is determined that the coaching style should not be changed; and providing feedback to the user during the workout session based on the coaching style.

Abstract: A delivery system is provided. In the delivery system, drones deliver items in a serviced area and charging stations are distributed throughout the serviced area. Each charging station is configured to charge one or more of the drones. The delivery system further includes a processor that is communicative with at least the charging stations. The processor is configured to dynamically route delivery operations of each of the drones in accordance with one or more parameters. The processor is further configured to communicate with individuals involved with the delivery operations in accordance with any of the charging stations being associated with the delivery operations.

Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target soring bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

Abstract: Three-dimensional positional spatial olfaction for virtual marketing associates a product with a product location within a virtual reality environment and identifies a product aroma associated with the product. A distance and a direction from the product location to a positional presence of a participant within the virtual reality environment is determined, and the product aroma is delivered to the participant in accordance with the distance and the direction. Delivery of the product aroma to the participant in accordance with the distance and the direction is used to lead the participant through the virtual reality environment to the product location where an interface for obtaining a physical copy of the product is displayed to the participant.

Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.

Abstract: Tooling apparatus and methods are provided to fabricate semiconductor devices in which controlled thermal annealing techniques are utilized to modulate microstructures of metallic interconnect structures. For example, an apparatus includes a single platform semiconductor processing chamber having first and second sub-chambers. The first sub-chamber is configured to receive a semiconductor substrate comprising a metallization layer formed on a dielectric layer, wherein a portion of the metallization layer is disposed within an opening etched in the dielectric layer, and to form a stress control layer on the metallization layer. The second sub-chamber comprises a programmable hot plate which is configured to perform a thermal anneal process to modulate a microstructure of the metallization layer while the stress control layer is disposed on the metallization layer, and without an air break between the process modules of forming the stress control layer and performing the thermal anneal process.

Abstract: A magnetic random access memory (MRAM) device includes a conductor disposed in an insulating material of a lower wiring layer, a magnetic tunnel junction (MTJ) structure formed in an upper wiring layer, and a landing pad formed in an intermediary wiring layer between the lower and upper wiring layers, the landing pad extending from a top surface of the conductor to a height above the intermediary wiring layer, wherein the landing pad connects the MJT structure to the conductor.

Abstract: Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack.