Abstract: A clamp for securing a tubular or hose-shaped object on a support. The clamp includes a clamp jacket having first and second ends, wherein a first leg protrudes from the first end of the clamp jacket and a second leg projects from the second end of the clamp jacket. The first leg has a lug which in the open state protrudes in the direction of the second leg. The second leg includes a fastening section which can be inserted into a gap between the lug and a neighboring portion of the first leg located opposite the lug, wherein, in the closed state of the clamp, the lug is plastically deformed toward the outer side of the fastening section facing away from the first leg.

Abstract: A non-volatile memory device includes a plurality of word lines, a plurality of sense lines, and a plurality of non-volatile memory cells. Each memory cell includes a floating gate transistor having a control gate, a floating gate separated dielectrically from the control gate, a drain connection and a source connection. The control gate is connected to one of the word lines and the source connection is connected to one of the sense lines, the drain connection being electrically isolated from the other memory cells. A method for reading the memory device and a method for operating the memory device are also provided.

Abstract: An electronic system employing a clock signal correcting device is disclosed. One embodiment provides a leading edge delay device incrementing leading edges with respect to trailing edges, a trailing edge delay device incrementing trailing edges with respect to the leading edges, and a correction delay device delaying the leading edges of clock pulses if a leading edge incrementing step is greater than a trailing edge incrementing step and delaying the trailing edges of the clock pulses if the leading edge incrementing step is greater than the trailing edge incrementing step.

Abstract: Collecting and distributing information related to recent content publication activity of an instant messaging (IM) user provides other users in a network with timely, relevant information about people known to the user or within the same social network. A user participating in a social network can quickly and efficiently perceive new information related to other users (referred to as co-users) in a social network by reviewing the co-users' recent content publication activity. A user may be made able to do so without requiring the co-user to send a communication directly to the user regarding the new facts or new content, and also without requiring the user to actively browse or request information about the co-user.

Abstract: Collecting and distributing information related to recent content publication activity of an instant messaging (IM) user provides other users in a network with timely, relevant information about people known to the user or within the same social network. A user participating in a social network can quickly and efficiently perceive new information related to other users (referred to as co-users) in a social network by reviewing the co-users' recent content publication activity. A user may be made able to do so without requiring the co-user to send a communication directly to the user regarding the new facts or new content, and also without requiring the user to actively browse or request information about the co-user.

Abstract: The present invention relates to a new method of preparing gaboxadol (THIP), which is useful for treating sleep disorders. In particular a method of preparing THIP comprising reacting a compound of formula (8b) or a salt thereof with an acid, typically a mineral acid, to obtain THIP as an acid addition salt. The present invention also relates to several intermediates.

Abstract: Method for fabricating a semiconductor memory device having auxiliary transistor structures which are required for lithography and etching processes. A protective structure for reducing leakage currents between gate conductor and doped zone is provided. The protective structure is formed as a region doped oppositely to the doped zone.

Abstract: An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.

Abstract: An integrated circuit includes a first and a second amplifier circuit each driven by an input signal. The first and second amplifier circuits generate a first and a second control signal on the output side. The control signals are generated independently of one another and drive a first and second controllable resistor of a third amplifier circuit for generating a third control signal. The third control signal is fed back to the first and second amplifier circuits. Depending on the resistance value of the first and second controllable resistors of the third amplifier circuit, an output signal amplified with respect to the input signal is generated at an output terminal of the integrated circuit. The integrated circuit is an input amplifier of an integrated semiconductor memory and permits the input signal to be amplified with a gain independent of a level of the DC component of the input signal.

Abstract: The invention relates to an unsaturated polyester resin mixture which can be cured by applying external pressure and which encompasses at least the following components: a) an unsaturated polyester resin whose weight-average molar mass is from 500 to 5000 g/mol; b) an ethylenically unsaturated monomer; c) a shrinkage-reducing component; d) an inert filler; and e) a reinforcing fibre; and f) from 0.01 to 1% by weight of a block copolymer, based on the total weight of the unsaturated polyester resin mixture comprising reinforcing fibre, where the block copolymer encompasses at least one A block and encompasses at least one B block, where the A block contains at least one amine-containing, ethylenically unsaturated monomer; and the B block contains at least one alkyl- and/or phenyl-containing, ethylenically unsaturated monomer, and is free from amine-containing, ethylenically unsaturated monomers.

Abstract: An electrostatic discharge-protected integrated circuit includes a transistor connected by one of the drain and source terminals to a first terminal that applies a first supply potential and by another of the drain and source terminals to a second terminal that applies a second supply potential. A first capacitor and a second capacitor are connected as a capacitive voltage divider between the first and second terminals. The common coupling node of the first and second capacitors is connected to the control terminal of the transistor. In a discharge mode, the transistor is conductive and thus short-circuits a voltage which is not suitable for normal operation of the functional circuit between the first and second terminals.

Abstract: An integrated circuit with electrostatic discharge protection includes a first transistor with a source terminal, a drain terminal and a gate terminal, and a second transistor with a source terminal, a drain terminal and a gate terminal. The gate terminal for each of the first and second transistors is connected to the drain terminal. The first transistor is connected in series with the second transistor by one of the drain and source terminals of the first transistor being connected to one of the drain and source terminals of the second transistor. The series circuit formed by the transistors is connected to an input terminal of the integrated circuit or to a supply terminal and a terminal that applies the reference potential of the integrated circuit. The series circuit of the transistors is dimensioned by the number of transistors and the setting of the channel length and channel width ratios of the transistors.

Abstract: The present invention provides a tool capable of being set and released without requiring the complexity of former tools. A novel arrangement of a push sleeve in the spring body eliminates the need for several shear pins while an internal J slot formed directly on the mandrel significantly reduces the size of the lower drag body and thus the length of the tool. These and other improvements to the packer tool result in a significantly simplified tool capable of meeting the full requirements of a production packer.

Abstract: A sense amplifier includes at least two field effect transistors of identical conductivity type, each including a gate terminal, a source terminal, a drain terminal and a bulk terminal. The two field effect transistors are connected such that they are coupled back-to-back between a bit line and a reference line. The bit line is connected to a memory node via a selection transistor. The field effect transistors include bulk or substrate terminals formed in mutually insulated, different wells. The substrate bias voltages and thus the threshold voltages can be set independently via the body effect, so that the threshold voltages that are fundamentally different on account of stochastic effects in the different wells can be adapted to one another. Thus, compensating for the disadvantages that occur in conventional wells, on account of scattering effects during implantation or on account of mechanical stresses which act differently on transistors that are otherwise formed uniformly in the same well.

Abstract: An integrated semiconductor memory (100) comprises a controllable voltage generator (30) for precharging bit lines (BL) of a memory cell array (10) to a precharge voltage (VEQ). During the read-out of a first and second memory state of memory cells (SZ) which are connected to the bit lines, a first and second signal swing (?UH, ?UL) occurs on the bit lines, as a result of which the bit lines are charged to a first and a second voltage potential (V1, V2). For the purpose of precharging the bit lines to the precharge voltage (VEQ), a first equalize current (I1) and a second equalize current (I2) are fed onto the bit lines by the controllable voltage generator (30), the current intensity of said currents in each case being measured by a detector circuit (60). A control circuit (20) alters the precharge voltage (VEQ) until the first and second equalize currents (I1, I2) have identical magnitudes. The precharge voltage is then centered with respect to the first and second voltage potentials (V1, V2).

Abstract: A means of attachment for electrically contacting electronic components is disclosed. The means of attachment includes a carrier element and a number of elongated connecting elements. Each of the connecting elements is arranged on the carrier element and has an elongated body, which protrudes from the carrier element. Each of the connecting elements and the carrier element includes an electrically conductive surface.

Abstract: A colored intercapsular buffer solution is used to reduce erroneous results from the absorption or carryover of small amounts of reagent R1 and/or R2 into the intercapsular buffer solution segment in the analytical line of a capsule chemistry liquid analysis system in an automated clinical analyzer. The absorption of small amounts of the regent R1 and/or R2 in the intercapsular buffer solution leads to erroneous results in the analysis of the test sample, S, because the R1 and/or R2 that is carried over and absorbed into the buffer does not react with test sample S. The R1/R2 carryover can be measured and determined by monitoring the absorbance of the colored buffer solution, wherein the change in absorbance can be measured and compared to a reference value. The sample is automatically retested if an unacceptable change in absorbance occurs.

Abstract: An ancillary reducing reagent composition is used to significantly reduce and substantially eliminate the incidence of false positive results in an immunoassay for the detection of antibodies to Hepatitis A virus. The reducing agent contained in the ancillary reducing reagent composition is a sulfhydryl compound buffered to a pH sufficient to prevent oxidation of the reducing agent.

Abstract: The invention relates to a method for producing a TFA image sensor in which a multi-layer arrangement comprising a photo diode matrix is arranged on an ASIC switching circuit provided with electronic circuits for operating the TFA image sensor, such as pixel electronics, peripheral electronics and system electronics, for the pixel-wise conversion of electromagnetic radiation into an intensity-dependent photocurrent, the pixels being connected to contacts of the underlying pixel electronics of the ASIC switching circuit. The method enables conventionally produced ASIC switching circuits to be used without impairing the topography of the photoactive sensor surface. The CMOS passivation layer in the photoactive region and then the upper CMOS metallization are removed and replaced by a metallic layer which is structured in the pixel raster, for the formation of back electrodes.

Abstract: An integrated semiconductor memory includes programmable elements, which are arranged in a continuous region on a chip area of the integrated semiconductor memory. Operating parameters, for example, word line addresses of defective word lines are stored in the programmable elements in a compressed data format during the fabrication process of the integrated semiconductor memory. Upon activation of the integrated semiconductor memory, the compressed data are read out by a read-out circuit and fed to a decompression circuit. The decompression circuit generates, from a bit sequence of the compressed data with the aid of a decompression algorithm, a bit sequence of decompressed data which are evaluated by a control circuit. The storage of the operating parameters in the compressed data format and the arrangement of the programmable elements in a compact region significantly reduce the space requirement on the semiconductor chip.