Abstract: A semiconductor memory is disclosed having an electrically conductive region buried in a substrate, and having an array of first and second cells. The first cells are designed as memory cells each having a selection transistor and a storage capacitor and are connected to word lines and first bit lines. The second cells are designed as switchable contacts each having a selection transistor and a resistance element and are connected to a respective one of the word lines and to a second bit line. The resistance element includes a first electrode and a second electrode, which are conductively connected to one another. The second bit line makes it possible to apply a plate voltage to the buried conductive region in low-impedance fashion via the second cells.

Abstract: An integrated semiconductor memory comprises a clock generator circuit (10), which is driven by an external clock signal (Cext) for the generation of an internal clock signal (Cint). The clock generator circuit (10) generates a level (PI1, PI2) of the internal clock signal if it is driven by the external clock signal with a level (PE1, PE2) for the duration of a sensitivity time (TE). The internal clock signal (Cint) has a higher frequency and phase stability than the external clock signal (Cext). The integrated semiconductor memory furthermore comprises a control circuit (20) for controlling the clock generator circuit (10), which is likewise driven by the external clock signal. The control circuit (20) alters the sensitivity time (TE) of the clock generator circuit (10) in a manner dependent on a frequency of the external clock signal. This prevents a noisy external clock signal (Cext) from leading to an uncontrolled switching behavior of an internal chip logic of the integrated semiconductor memory.

Abstract: An integrated circuit includes a voltage generator with a first controllable resistor and a second controllable resistor, through which a first input terminal that applies a first voltage potential and a second input terminal that applies a second voltage potential can be connected to an output terminal that generates an output voltage. In a manner dependent on the output voltage, a first comparator circuit generates a first control signal to control the first controllable resistor, and a second comparator circuit generates a second control signal to control the second controllable resistor. A control unit evaluates the control signals generated by the comparator circuits and drives the first and second controllable resistors of the voltage generator in such a way that in each case only one of the two controllable resistors has a low-resistance state.

Abstract: The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection or substrate connection.

Abstract: The present invention relates to warning systems, and more particularly to public advance warning system to occupants of non-emergency vehicles of the presence of an active emergency vehicle in the vicinity. The present invention can be used to enhance the awareness of drivers and passengers of non-emergency vehicles who travelling near or in the path of emergency vehicles that are active in response to an emergency. The present invention utilizes audio-visual warning in order to indicate that active emergency vehicles are in the vicinity. The present invention is particularly adaptable to be integrated into the instrument panel of non-emergency automobiles or as a stand-alone warning system inside the non-emergency automobile.

Abstract: The invention relates a substrate for a package for an electronic circuit and methods for packaging an electronic circuit with a substrate. The substrate comprises at least one conduction region and an activation region arranged within the substrate. The activation region is generally in contact with the conduction region and is configured to change its electrical resistance when activation occurs.

Abstract: The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The large extent of the channel region in the bit line direction means that the trench capacitor can be rapidly charged and read. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. A conductive channel can be formed within the channel region depending on the potential of the word line.

Abstract: An integrated circuit includes a first and a second amplifier circuit (10, 20), which are in each case driven by an input signal (Vin) having a high and a low signal level and a reference signal (Vref) having a constant signal level and, on the output side (D11, D21) generate a first control signal (S1) and a second control signal (S2). The control signals (S1, S2) are generated independently of one another and are used to regulate a first controllable resistor (31) and a second controllable resistor (32) of a third amplifier circuit (30). Depending on the resistance value of the first and second controllable resistors (31, 32) of the third amplifier circuit, an output signal (Vout) that is amplified in comparison with the input signal (Vin) can be generated at an output terminal (A). The integrated circuit can be used as an input amplifier of an integrated semiconductor memory and permits an adaptive behavior of the input amplifier with regard to fluctuations of the average absolute input signal level.

Abstract: A metallization surface (5), which acts as an etching stop layer during the production of openings (4) in a passivation layer (3) applied to its upper face and protects an interconnect structure (6) arranged underneath it, is arranged in an uppermost metallization level (1). A further opening is produced in the metal surface (5), through which a focused ion beam is aimed at the interconnect structure (6) in order to connect interconnects to one another and/or to interrupt at least one interconnect. The wiring of the integrated circuit can thus be varied individually, starting from identically produced semiconductor chips.

Abstract: In a DRAM memory circuit, the sense amplifiers, for amplifying the differential voltage sensed between the cores of a bit line, in each case contain two transistor circuits, each of which has two switching transistors. The first transistor circuit pulls the lower potential of the sensed differential voltage down to a defined low logic potential. The second transistor circuit pulls the higher potential up to a defined high logic potential. According to the invention, all the transistors in the sense amplifier are field-effect transistors of the same conduction type, in the case of which the channel is at low impedance if the gate potential is higher than the source potential at least by the amount of the threshold voltage Vth.

Abstract: The invention relates to a method for controlling the reading-in of a data signal at an input of an electrical circuit to an input latch with the aid of a clock signal, with the data item, which is indicated by the data signal, being transferred to the input latch with a clock edge of the clock signal, with the clock edge of the clock signal being shifted in time as a function of a time delay between a signal edge of the input signal at the input and the clock edge, such that the time delay between the signal edge of the data signal and the clock edge is within a predetermined time window.

Abstract: An integrated semiconductor memory includes a sense amplifier with a first subamplifier for driving memory cells of a first memory cell array and a second subamplifier for driving memory cells of a second memory cell array. The subamplifiers are connected via continuous lines to bit lines of the first memory cell array and to bit lines of the second memory cell array. The subamplifiers can be operated by applying a single control signal (MUX1, MUXr) in a first operating state for reading in, reading out, and refreshing information of the memory cells and in a second operating state for precharging the bit lines. Reduction of the signal line due to losses is avoided as a result of direct coupling the subamplifiers to the respective memory cell arrays.

Abstract: An integrated circuit has a voltage divider that is configured to save current. The circuit includes a capacitor that is inventively connected to a potential sink or potential source by way of a charge branch even when the voltage divider is inactive. The capacitor is thus held at a charge state that corresponds to the charge state given an active voltage divider. The voltage divider thus becomes functional in a shorter time following activation, because the capacitor does not require recharging.

Abstract: The present invention provides a tool capable of being set and released without requiring the complexity of former tools. A novel arrangement of a push sleeve in the spring body eliminates the need for several shear pins while an internal J slot formed directly on the mandrel significantly reduces the size of the lower drag body and thus the length of the tool. These and other improvements to the packer tool result in a significantly simplified tool capable of meeting the full requirements of a production packer.

Abstract: A receiver circuit arrangement contains a receiver circuit (2) having an input (201) for receiving an input signal (IN), having an output (202) for outputting an output signal (OUT_F) and having an inverter circuit (21, 22, 23) having switching transistors (211, 212), to which the input signal is fed, at least one control transistor (221, 222) being connected in series with the switching transistors. A control circuit (3) is connected, on the input side, to a terminal for a reference voltage (VREF) and, on the output side, to the control terminal of the control transistor (221, 222) of the inverter circuit. The control circuit (3) is designed in such a way that the control transistor (221, 222) is driven by the regulating switching circuit in the event of deviations of the reference voltage (VREF) from a voltage value in a reference operating state with a control voltage (VCTL1, VCTL2) that deviates with respect to the reference operating state.

Abstract: An apparatus (1) for testing a memory module (2) suitable for exchanging electrical signals with a motherboard (10) contains a device (8a-8k) suitable for detecting the operating state of at least one semiconductor chip (26a-26m) of the module, which device comprises a first set of signal lines (8a-8k), a microcontroller (3) with a memory device (32) for storing the operating state, said microcontroller being electrically connected to the signal lines (8a-8k), a clock generator (5) suitable for generating an operating clock, said clock generator being electrically connected to the microcontroller (3), and a signal connection (13) suitable for communicating a signal for controlling access to the memory module (2) between the circuit board arrangement (10) and the microcontroller (3) and for communicating to the microcontroller (3) a signal for initiating a process of detecting the operating state.

Abstract: An integrated semiconductor memory can have a memory cell with a storage capacitor and a selection transistor, which can be driven by a bit line and a word line. The selection transistor can have a region made of semiconductor material, which adjoins a gate dielectric, in which a transistor channel can be formed, and into which is introduced a source/drain implantation with which electrical contact is made by the bit line. A Schottky contact is provided between the selection transistor and the storage capacitor. The region made of semiconductor material is free of dopants of a source/drain implantation proximate to the Schottky contact. By dispensing with a source/drain implantation on the capacitor side, leakage currents are reduced and the write and read-out speed of the memory cell is increased.

Abstract: An ESD protection apparatus for limiting a voltage superimposed on an electric useful voltage to an allowable voltage, comprising a plurality of series-connected diodes. The diodes are forward-biased with reference to the useful voltage. Each individual forward-biased diode has a threshold voltage. The sum of the threshold voltages of the series-connected diodes corresponds to the allowable voltage.

Abstract: The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. As a result, a conductive channel can be formed within the channel region depending on the potential of the word line. Preferably, the extent of the trench hole in the word line direction is at least 1.5 times as large as in the bit line direction.

Abstract: An integrated memory includes memory cells arranged in a memory cell array along word lines and bit lines. One of the bit lines can be connected to a data line by a respective one of a plurality of switches. The memory contains column select lines. One of the column select lines in each case connected to a plurality of the switches for driving, in an activated state, in order to connect a number of bit lines to a same number of data lines. An access controller is connected to the column select lines and can be operated in a test operating mode such that a plurality of the column select lines are activated in the event of a memory cell access. The writing of test data to the memory cell array in a test operating mode can thus be optimized in accordance with the invention.