Abstract: Embodiments of the present disclosure provide an apparatus including: a phase detector for detecting a write frequency of a deserializer and a read frequency of a serializer, such that the phase detector outputs a first code sequence in response to the write frequency being greater than the read frequency, or a second code sequence at the rotator input in response to the write frequency being less than the read frequency; and a phase rotator for receiving the first code sequence or the second code sequence from the phase rotator to transmit a pacing signal having the read frequency to the deserializer, wherein the pacing signal causes the read frequency to increase or decrease based on whether the read frequency is different from the write frequency.

Abstract: Embodiments of the present disclosure provide an apparatus including: a phase detector for detecting a write frequency of a deserializer and a read frequency of a serializer, such that the phase detector outputs a first code sequence in response to the write frequency being greater than the read frequency, or a second code sequence at the rotator input in response to the write frequency being less than the read frequency; and a phase rotator for receiving the first code sequence or the second code sequence from the phase rotator to transmit a pacing signal having the read frequency to the deserializer, wherein the pacing signal causes the read frequency to increase or decrease based on whether the read frequency is different from the write frequency.

Abstract: A system and method for receiving includes an input multiplexer configured to select between one or more input data streams and a pseudo random bit sequence (PRBS) to provide a serial stream. A plurality of storage devices is configured to sample the serial stream. An output demultiplexer is configured to demultiplex the sampled serial stream into a plurality of output streams. A PRBS checker is configured to compare a PRBS pattern on the plurality of output streams with a predicted PRBS pattern. A phase rotator is configured to adjust a data control clock based upon the comparison of the PRBS checker to reduce latency in the receiver.

Abstract: A system and method for transmitting includes a plurality of multiplexers each configured to combine a pseudo random bit sequence (PRBS) with at least one input stream according to the data control clock. At least one storage device is coupled to an output of each of the plurality of multiplexers and is configured to latch data according to the data control clock. An output multiplexer is coupled to each of the at least one storage device and is configured to select between storage paths according to the data serializer clock. A PRBS checker is configured to compare a PRBS pattern on an output of the output multiplexer with a predicted PRBS pattern. A phase rotator is configured to adjust the data serializer clock based upon the comparison of the PRBS checker to reduce latency of the transmitter.

Abstract: A system and method for transmitting includes a plurality of multiplexers each configured to combine a pseudo random bit sequence (PRBS) with at least one input stream according to the data control clock. At least one storage device is coupled to an output of each of the plurality of multiplexers and is configured to latch data according to the data control clock. An output multiplexer is coupled to each of the at least one storage device and is configured to select between storage paths according to the data serializer clock. A PRBS checker is configured to compare a PRBS pattern on an output of the output multiplexer with a predicted PRBS pattern. A phase rotator is configured to adjust the data serializer clock based upon the comparison of the PRBS checker to reduce latency of the transmitter.

Abstract: A system and method for receiving includes an input multiplexer configured to select between one or more input data streams and a pseudo random bit sequence (PRBS) to provide a serial stream. A plurality of storage devices is configured to sample the serial stream. An output demultiplexer is configured to demultiplex the sampled serial stream into a plurality of output streams. A PRBS checker is configured to compare a PRBS pattern on the plurality of output streams with a predicted PRBS pattern. A phase rotator is configured to adjust a data control clock based upon the comparison of the PRBS checker to reduce latency in the receiver.

Abstract: Multi-protocol driver slew rate calibration systems for calibrating slew rate control signal values are provided. Embodiments include generating, by a first phase rotator, a first clock signal; generating, by the second phase rotator, a second clock signal; initially setting, by a calibration controller, phase selector amounts such that the first clock signal is delayed relative to the second clock signal; determining whether the first clock signal is delayed relative to the second clock signal; if the first clock signal is delayed, changing the second phase selector amount; and if the first clock signal is not delayed, using the first clock signal and the second clock signal to calibrate values of control signals provided to control a slew rate of a calibration clock delay line such that the slew rate of the calibration clock delay line substantially matches a target slew rate.

Abstract: A slew rate control circuit configured to control a slew rate of driver circuit comprises a clock delay module that receives a half-rate clock signal and that includes a plurality of delay cells configured to generate a plurality of respective delayed clock signals each having a different time delay from one another. A driver module includes a plurality of multiplexers in electrical communication with a respective data cell to receive a corresponding delayed clock signal. The multiplexers are configured to output a respective full-rate data stream in response to the delayed clock signal. The slew driver module further includes an output stage circuit in electrical communication with each multiplexer to combine each full-rate data stream and to generate a final step-wise driving signal that controls the slew rate.

Abstract: A slew rate control circuit configured to control a slew rate of driver circuit comprises a clock delay module that receives a half-rate clock signal and that includes a plurality of delay cells configured to generate a plurality of respective delayed clock signals each having a different time delay from one another. A driver module includes a plurality of multiplexers in electrical communication with a respective data cell to receive a corresponding delayed clock signal. The multiplexers are configured to output a respective full-rate data stream in response to the delayed clock signal. The slew driver module further includes an output stage circuit in electrical communication with each multiplexer to combine each full-rate data stream and to generate a final step-wise driving signal that controls the slew rate.

Abstract: A multi-use physical (PHY) architecture that includes a PHY connection that includes one or more bit lines and that is communicatively coupled to a first processor. The PHY connection is configurable to carry signals between the first processor and a second processor, or between the first processor and a memory. The one or more bit lines are configured to carry signals bi-directionally at a first voltage when the PHY connection is configured to carry signals between the first processor and the memory. The one or more bit lines are configured to carry signals uni-directionally at a second voltage when the PHY connection is configured to carry signals between the first processor and the second processor. The second voltage is different than the first voltage.

Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

Abstract: Leakage tolerant delay locked loop (DLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant DLL circuit device are provided. Embodiments include a DLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, and a voltage controlled buffer (VCB). The secondary correction circuit is configured to generate and provide secondary error-delay signals to the error controller. The secondary correction circuit includes multiple error generators. Each error generator is configured to generate a secondary error-delay signal in response to detecting a particular edge of an output phase signal from the VCB. The primary loop is configured to control a phase adjustment based on at least one of a first error-delay-increase signal, a first error-delay-decrease signal, and the secondary error-delay signals.

Abstract: Leakage tolerant delay locked loop (DLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant DLL circuit device are provided. Embodiments include a DLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, and a voltage controlled buffer (VCB). The secondary correction circuit is configured to generate and provide secondary error-delay signals to the error controller. The secondary correction circuit includes multiple error generators. Each error generator is configured to generate a secondary error-delay signal in response to detecting a particular edge of an output phase signal from the VCB. The primary loop is configured to control a phase adjustment based on at least one of a first error-delay-increase signal, a first error-delay-decrease signal, and the secondary error-delay signals.

Abstract: Leakage tolerant phase locked loop (PLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant PLL circuit device are provided. Embodiments include a PLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, a voltage controlled oscillator (VCO), and feedback divider. The secondary correction circuit is configured to generate and provide a secondary error-frequency signal to the error controller. The secondary correction circuit is configured to generate the secondary error-frequency signal in response to detecting a particular edge of a divided VCO output signal. The primary loop is configured to control a frequency adjustment based on at least one of a first error-frequency-increase signal, a first error-frequency-decrease signal, and the secondary error-frequency signal.

Abstract: A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.

Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

Abstract: A multi-use physical (PHY) architecture that includes a PHY connection that includes one or more bit lines and that is communicatively coupled to a first processor. The PHY connection is configurable to carry signals between the first processor and a second processor, or between the first processor and a memory. The one or more bit lines are configured to carry signals bi-directionally at a first voltage when the PHY connection is configured to carry signals between the first processor and the memory. The one or more bit lines are configured to carry signals uni-directionally at a second voltage when the PHY connection is configured to carry signals between the first processor and the second processor. The second voltage is different than the first voltage.

Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

Abstract: A phase locked loop (“PLL”) includes a voltage controlled oscillator (“VCO”) operable to acquire and maintain lock at a selected output frequency of the VCO and control logic operable to perform steps in a method of selecting a frequency band for operating the VCO.

Abstract: A method is provided for selecting an operating band of a voltage-controlled oscillator (“VCO”) of a phase locked loop (“PLL”) for which the lock frequency is closest to a center of the frequency range of the operating band. In such method, steps can be performed to determine the maximum and minimum frequencies of the operating band and the center frequency between them. From the center frequency of the operating band and the lock frequency within such operating band, a difference value can then be determined. The operating bands of the PLL can be tested until an operating band having the smallest difference value is determined. The VCO can then be set to such operating band in order for the lock frequency to be closest to the center frequency of the operating band.