Abstract: A structure and method for damping LC (inductance-capacitance) ringing in integrated circuit (IC) power distribution systems. The structure comprises a resistance electrically connected in parallel with a plurality of electrical switches. The resistance and electrical switches are electrically connected in series with the package and on-chip power distribution circuit. When on-chip switching activity creates a sudden and appreciable change in IC power demand the electrical switches are opened to temporarily increase the resistance in series with the power supply. This serves to dampen the power-distribution LC ringing. Later, the electrical switches are closed to shunt the series resistance and reduce the level of steady-state voltage drop in the power structure.

Abstract: A circuit, including: a capacitor coupled between a first circuit node and a second circuit node and that leaks a leakage current from the first circuit node to the second circuit node; and a compensation circuit adapted to supply a compensatory current to compensate for the leakage current to the first circuit node.

Abstract: As disclosed herein, systems and methods are provided for generating and distributing a plurality of reference currents on an integrated circuit. In a particular embodiment, an integrated circuit is disclosed which includes a reference current generator adapted to generate a plurality of reference currents. Such circuit includes an operational amplifier coupled to receive, at a first polarity input, a reference voltage, and a first transistor Q1 having a biasing input coupled to an output of the operational amplifier. The first transistor also has an output coupled to a fixed potential through a first resistor R1, and the output of the first transistor Q1 is further coupled as feedback to a second polarity input of the operational amplifier. One or more second transistors Qi are provided in the circuit, each of which has a biasing input coupled to the output of the operational amplifier, and an output coupled to the fixed potential through a respective second resistor Ri.

Abstract: An apparatus is provided for measuring an output of a high-speed data transmission circuit. The apparatus includes a programmable reference voltage generator operable to generate a reference voltage that is variable between a plurality of levels. The apparatus also includes a quantizer to quantize an output of the high-speed data transmission circuit relative to the reference voltage level input thereto. Also included is a clock generator operable to generate a clock having a transitioning time (rise-time, fall-time or both) that is less than one quarter of a minimum switching period of the output of the circuit. Finally, the apparatus includes a sampler operable to sample the quantized output with the clock to produce a plurality of samples which measure the output of the circuit.

Abstract: Apparatus and method for counteracting high frequency attenuation of a differential input data signal as the signal is conducted through a data link. A differential input data signal is transmitted from a transmitter to a receiver through a data link. The data eye of the differential input data signal is modified at the transmitter in response to feedback from the receiver where the extent of the data eye of the differential input data signal, after being conducted through the data link, is determined. The feedback to the transmitter, dependent on the determination of the extent of the data eye, controls the data eye at the transmitter and the equalization of the differential input data signal by adapting the differential input data signal to anticipate high frequency attenuation of the differential input data signal in the data link.

Abstract: Methods and structures are disclosed herein for programmably adjusting a peaking function of a differential signal receiver. The disclosed method includes inputting a pair of differential signals to a pair of input transistors coupled to conduct currents differentially between a pair of load impedances and a pair of tail transistors. The impedance of an adjustable shunt impedance element between the tail transistors of the receiver is varied by programming signal input, such that higher current is conducted over a peaking range of frequencies. In a disclosed structural embodiment, an integrated circuit is provided having a programmable peaking receiver. The programmable peaking receiver includes a pair of input transistors coupled to conduct differentially according to a pair of differential inputs applied to the pair of input transistors. Each of the input transistors produces an output in accordance with the differential input applied thereto.

Abstract: A method and system are disclosed herein for determining optimum power level settings for a transmitter and receiver pair of a communication system having a plurality of transmitter and receiver pairs, as determined with respect to bit error rate. In the method disclosed herein, the power levels of a transmitter and a receiver pair coupled to communicate over a duplex communication link are set to initial values. The bit error rate is then determined over the link. Then, the power level of the transmitter, the receiver, or both, is altered, incrementally, and the effect upon the bit error rate is determined. When an improvement appears in the bit error rate at an altered power level, the power level of the transmitter, the receiver or both, are set to the altered power level at which the improvement is found.

Abstract: As disclosed herein, systems and methods are provided for generating and distributing a plurality of reference currents on an integrated circuit. In a particular embodiment, an integrated circuit is disclosed which includes a reference current generator adapted to generate a plurality of reference currents. Such circuit includes an operational amplifier coupled to receive, at a first polarity input, a reference voltage, and a first transistor Q1 having a biasing input coupled to an output of the operational amplifier. The first transistor also has an output coupled to a fixed potential through a first resistor R1, and the output of the first transistor Q1 is further coupled as feedback to a second polarity input of the operational amplifier. One or more second transistors Qi are provided in the circuit, each of which has a biasing input coupled to the output of the operational amplifier, and an output coupled to the fixed potential through a respective second resistor Ri.

Abstract: An apparatus for capturing a data signal sent from a transmitting source to a receiving element, the data signal being accompanied by a first clock signal in a source synchronous system. In an exemplary embodiment, the apparatus comprises a delay element having an input coupled to the first clock signal and an output producing a delayed first clock signal. The delay element further includes a plurality of delay latches, having a second clock signal as a clock input thereto, the second clock signal having a frequency which is a multiple of the frequency of the first clock signal. The data signal is captured by the receiving element when the receiving element is triggered by an edge of the delayed first clock signal.

Abstract: A transmitter for driving a transmission medium employs pre-distortion to predistort the signals leaving the driver so that they will have an acceptable shape when they reach their destination and have been distorted by imperfections in the transmission medium. The change to pulse height is accomplished by means of a current steering unit that directs a controllable amount of current into the line for each pulse while maintaining the total sum of current that is generated constant in order to reduce noise. Control coefficients for the current steering unit are manipulated in an nxm register that automatically maintains the total number of bits constant while bits are moved from a location that controls a first current driver to a location that controls a second current driver with different properties.

Abstract: A data communication system includes circuitry to assure components respond to variations in the time length of the valid data window or “eye” of the high speed data communication signal. A self-test portion of the system periodically injects the effects of phase jitter into the data communication signal to assure the system performs properly.

Abstract: A calibration system for a Phase Locked Loop (PLL) includes a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency. A charge pump is connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter. The low pass filter provides a filtered error signal to the VCO and to a comparator system. The comparator system provides a comparator output signal indicating when the polarity of the error signal exceeds a positive limit or a negative limit. A calibration means continuously provides incremental calibration inputs to the VCO, after a time delay. Thus the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift, and avoid jitter caused by an excessive rate of response to calibration inputs.

Abstract: An on-chip system and method for measuring the jitter tolerance of a clock and data recovery loop is disclosed herein. Such clock and data recovery loop determines a clock phase for sampling a data stream on a data line by examining transitions of the data stream.

Abstract: A calibration system for a Phase Locked Loop (PLL) includes a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency. A charge pump is connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter. The low pass filter provides a filtered error signal to the VCO and to a comparator system. The comparator system provides a comparator output indicating when the polarity of the error signal exceeds a positive limit or a negative limit. A calibration means continuously provides incremental calibration inputs to the VCO after a time delay. Thus the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift and avoid jitter caused by an excessive rate of response to calibration inputs.

Abstract: An optical transceiver with a transimpedance amplifier generates a dynamic common mode voltage of the peak-to-peak output current of the photodetector for use as an in-situ optical power meter. Peak-to-peak voltage signal are imposed on the common mode voltage so optical power measurements are obtained using preexisting electrical contacts. An nfet and a capacitor of the transimpedance amplifier smooths the peak-to-peak voltage to create the control signal for the common mode voltage. The common mode current is mirrored into a bank of pfets at the output stage to create a current sink. Depending upon the potential of the common mode voltage, more or less current will be drawn from the peak-to-peak voltage signals output from a final differential amplifier stage of the transimpedance amplifier.

Abstract: An apparatus for capturing a data signal sent from a transmitting source to a receiving element, the data signal being accompanied by a first clock signal in a source synchronous system. In an exemplary embodiment, the apparatus comprises a delay element having an input coupled to the first clock signal and an output producing a delayed first clock signal. The delay element further includes a plurality of delay latches, having a second clock signal as a clock input thereto, the second clock signal having a frequency which is a multiple of the frequency of the first clock signal. The data signal is captured by the receiving element when the receiving element is triggered by an edge of the delayed first clock signal.

Abstract: A voltage controlled oscillator of a phase locked loop circuit having digitally controlled gain compensation. The digital control circuitry provides binary logic input to the voltage controlled oscillator for a digitally controlled variable resistance circuit, a digitally controlled variable current transconductor circuit, or differential transistor pairs having mirrored circuitry for adjusting the V-I gain.

Abstract: An optical transceiver having a transimpedance amplifier with an in-situ optical power meter is disclosed which realizes that the common mode voltage of a peak-to-peak voltage signal derived from impinging light is related to the optical power of the impinging light. The peak-to-peak voltage signals, moreover, can be imposed on the common mode voltage so that the optical power measurements can be derived with existing electrical contacts. In the preferred embodiment, the optical power meter takes advantage of certain functions within a transimpedance amplifier of the optical receiver. First, the use of an nfet and a capacitor smooth the peak-to-peak voltage to create the control signal for the common mode voltage. Then the common mode current is mirrored into a bank of pfets at the output stage to create a current sink.

Abstract: A voltage controlled oscillator of a phase locked loop circuit having digitally controlled gain compensation. The digital control circuitry provides binary logic input to the voltage controlled oscillator for a digitally controlled variable resistance circuit, a digitally controlled variable current transconductor circuit, or differential transistor pairs having mirrored circuitry for adjusting the V-I gain.

Abstract: A clock encoding circuit, e.g., for Manchester encoding, for high speed data transmission (IEEE 1394) and a circuit for controlling data and encoded clock transmission. The clock encoding circuit includes two parallel to serial shift registers, a DATA register and a STROBE register, receiving data in parallel and shifted out at 100 MHz, 200 MHz or 400 MHz. The STROBE register receives every other bit of the data inverted. When both registers are clocked at the data transmission rate, data is shifted out of DATA register and the transmission clock is encoded in STROBE, shifted out of the STROBE register. Bit inversion may be with invertors receiving data as it is passed to the DATA register, or alternatively, after it is loaded into the DATA register. The circuit for controlling DATA and STROBE transmission includes the clock encoding circuit, a frequency matching register array and a loopback shift register.