Patents by Inventor Michael Sorna
Michael Sorna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8144726Abstract: A design structure is provided for a microelectronic serial driver. The serial driver is operable to transmit a differential pattern signal during a burst interval and a predetermined common mode voltage level during a second interval between adjacent burst intervals, the serial driver including at least one pre-driver and a driver coupled to an output of the pre-driver for transmitting the differential communication signal. A switching circuit is operable to switch the serial driver between a first power supply voltage level for the burst interval and the predetermined common mode voltage level, wherein the predetermined common mode voltage level is independent of variations in power supply voltage conditions and temperature conditions.Type: GrantFiled: May 27, 2008Date of Patent: March 27, 2012Assignee: International Business Machines CorporationInventors: Huihao Xu, Joseph Natonio, James D. Rockrohr, Michael A. Sorna
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Patent number: 8126045Abstract: A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period.Type: GrantFiled: August 29, 2008Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: John Francis Bulzacchelli, Gautam Gangasani, Mounir Meghelli, Sergey V. Rylov, Michael A. Sorna, Steven J. Zier
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Patent number: 8040813Abstract: An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling element includes an isolating circuit coupled to the first conductor, a second conductor operable to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. The signal-handling circuit is operable to perform a signal-handling function in response to the output of the isolating circuit. By virtue of the isolating circuit, the signal-handling circuit and the first circuit are isolated from the second conductor and the signal-handling circuit. Preferably, the achieved isolation permits a communication signal included in the first signal to be conducted within a communication apparatus with less capacitance, and producing less return loss of that signal.Type: GrantFiled: June 2, 2005Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Karl D. Selander, Michael A. Sorna, Daniel W. Storaska
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Patent number: 8024679Abstract: A design structure for a signal-handing apparatus or communication apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. A signal-handling apparatus may include an isolating circuit coupled to a first conductor, a second conductor to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. A signal-handling circuit can perform a signal-handling function in response to the output of the isolating circuit. The signal-handling circuit and the first circuit may be isolated from the second conductor and the signal-handling circuit such that a communication signal may be conducted with less capacitance and be subject to less return loss.Type: GrantFiled: December 6, 2007Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Karl D. Selander, Michael A. Sorna, Daniel W. Storaska
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Publication number: 20110199843Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.Type: ApplicationFiled: February 15, 2010Publication date: August 18, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel M. Dreps, Kevin C. Gower, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann, James A. Mossman, Michael A. Sorna, Robert B. Tremaine, William M. Zevin
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Publication number: 20110188566Abstract: A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.Type: ApplicationFiled: February 2, 2010Publication date: August 4, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Troy J. Beukema, William R. Kelly, Michael A. Sorna, Daniel W. Storaska
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Patent number: 7974304Abstract: An integrated microelectronic serial driver is provided which is operable to transmit a differential pattern signal during a burst interval and a predetermined common mode voltage level during a second interval between adjacent burst intervals, the serial driver including at least one pre-driver and a driver coupled to an output of the pre-driver for transmitting the differential communication signal. A switching circuit is operable to switch the serial driver between a first power supply voltage level for the burst interval and the predetermined common mode voltage level, wherein the predetermined common mode voltage level is independent of variations in power supply voltage conditions and temperature conditions.Type: GrantFiled: June 7, 2007Date of Patent: July 5, 2011Assignee: International Business Machines CorporationInventors: Huihao Xu, Joseph Natonio, James D. Rockrohr, Michael A. Sorna
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Patent number: 7873922Abstract: A design structure embodied in a machine-readable medium used in a design process may include a system for detecting a fault in a signal transmission path. Such system may include, for example, a hysteresis comparator including a latch having n-type field effect transistor (“NFET”) storage elements. The hysteresis comparator may be operable to detect a crossing of a reference voltage level by an input signal arriving from the signal transmission path such that when the comparator does not detect an expected crossing of the reference voltage level by the input signal, the fault is determined to be detected in the signal transmission path.Type: GrantFiled: November 19, 2007Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Huihao Xu, Louis L. Hsu, Kevin G. Kramer, James D. Rockrohr, Michael A. Sorna
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Patent number: 7869544Abstract: An eyewidth of a data signal is determined by steps including: (a) recovering a phase of a clock from a data signal as a sampling clock; (b) shifting the phase of the sampling clock away from the first phase by a count multiplied by predetermined phase amount; (c) sampling the data signal with the shifted sampling clock phase to obtain sample data; d) determining whether the sample data contains error; (e) when the sample data does not contain error, recovering the phase of the clock from the data signal again for use as the first phase of the sampling clock, increasing the count value and repeating steps (b) through (e); and f) when the sample data contains error, determining the eyewidth based on the last shifted phase of the sampling clock prior to determining that the sample data contains error.Type: GrantFiled: January 3, 2008Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Michael A. Sorna, William R. Kelly, Daniel W. Storaska
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Patent number: 7855563Abstract: A system is provided for detecting a fault in a signal transmission path. In one embodiment, the system can include a variable amplitude signal attenuator which is operable to modify an input signal by variably attenuating a signal voltage swing of the input signal. Desirably, the input signal is attenuated only when transitioning from a high signal voltage level towards a low signal voltage level d variably, such that a larger high-to-low signal voltage swing is attenuated more than a smaller high-to-low signal voltage swing. Desirably, a comparator, which may apply hysteresis to the output signals, may detect a crossing of a reference voltage level by the modified input signal. In this way, when the comparator does not detect an expected crossing of the reference voltage level by the modified input signal, a determination can be made that a fault exists in the signal transmission path.Type: GrantFiled: June 21, 2007Date of Patent: December 21, 2010Assignee: International Business Machines CorporationInventors: Huihao Xu, Louis L. Hsu, Kevin G. Kramer, James D. Rockrohr, Michael A. Sorna
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Patent number: 7840916Abstract: A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined.Type: GrantFiled: November 19, 2007Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Hayden C. Cranford, Jr., Oleg Gluschenkov, James S. Mason, Michael A. Sorna, Chih-Chao Yang
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Patent number: 7772918Abstract: An apparatus and method for a regulated voltage boost charge pump for an integrated circuit (IC) device. The charge pump generally includes a plurality of switching networks and a lift capacitor that are intermittently coupled to an output capacitor or to a regulating transistor, a differential error amplifier biasing a gate terminal of the transistor, and a controller configured to alternate states of switches in the switching networks in a pre-selected timing relationship with a clock signal of the IC device.Type: GrantFiled: April 16, 2008Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: John A. Fifield, Bradford Hunter, Todd M. Rasmus, Michael A. Sorna, Daniel W. Storaksa
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Publication number: 20100194482Abstract: A method is provided for selecting an operating band of a voltage-controlled oscillator (“VCO”) of a phase locked loop (“PLL”) for which the lock frequency is closest to a center of the frequency range of the operating band. In such method, steps can be performed to determine the maximum and minimum frequencies of the operating band and the center frequency between them. From the center frequency of the operating band and the lock frequency within such operating band, a difference value can then be determined. The operating bands of the PLL can be tested until an operating band having the smallest difference value is determined. The VCO can then be set to such operating band in order for the lock frequency to be closest to the center frequency of the operating band.Type: ApplicationFiled: February 5, 2009Publication date: August 5, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel W. Storaska, Michael A. Sorna
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Publication number: 20100194483Abstract: A phase locked loop (“PLL”) includes a voltage controlled oscillator (“VCO”) operable to acquire and maintain lock at a selected output frequency of the VCO and control logic operable to perform steps in a method of selecting a frequency band for operating the VCO.Type: ApplicationFiled: February 5, 2009Publication date: August 5, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: DANIEL W. STORASKA, MICHAEL A. SORNA
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Patent number: 7733964Abstract: In a method for performing equalization of a communication system, a predetermined signal can be transmitted from a transmitter unit to a receiver unit in a downchannel direction on a transmission line, for example as a pair of differential signals which simultaneously transition in opposite directions on respective signal conductors of the transmission line. At the receiver unit, an eye opening of the signal received from the transmission line can be analyzed to determine equalization information. Equalization information can be transmitted from the receiver unit to the transmitter unit in an upchannel direction on the transmission line and be received at the transmitter unit. Using received equalization information, a transmission characteristic of the transmitter unit can be adjusted.Type: GrantFiled: October 17, 2007Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Karl D. Selander, Michael A. Sorna, Jeremy K. Stephens, Huihao Xu
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Patent number: 7719302Abstract: A method is provided for monitoring interconnect resistance within a semiconductor chip assembly, A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition.Type: GrantFiled: June 30, 2008Date of Patent: May 18, 2010Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Hayden C. Cranford, Jr., Oleg Gluschenkov, James S. Mason, Michael A. Sorna, Chih-Chao Yang
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Patent number: 7680179Abstract: A data communication system includes circuitry to assure components respond to variations in the time length of the valid data window or “eye” of the high speed data communication signal. A self-test portion of the system periodically injects the effects of phase jitter into the data communication signal to assure the system performs properly.Type: GrantFiled: August 29, 2007Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Jon David Garlett, Victor Moy, Michael A. Sorna
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Publication number: 20100054324Abstract: A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of the sense amplifiers during a precharge period. A gating circuit is configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period.Type: ApplicationFiled: August 29, 2008Publication date: March 4, 2010Inventors: John Francis Bulzacchelli, Gautam Gangasani, Mounir Meghelli, Sergey V. Rylov, Michael A. Sorna, Steven J. Zier
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Publication number: 20090300562Abstract: A design structure is provided for a microelectronic serial driver. The serial driver is operable to transmit a differential pattern signal during a burst interval and a predetermined common mode voltage level during a second interval between adjacent burst intervals, the serial driver including at least one pre-driver and a driver coupled to an output of the pre-driver for transmitting the differential communication signal. A switching circuit is operable to switch the serial driver between a first power supply voltage level for the burst interval and the predetermined common mode voltage level, wherein the predetermined common mode voltage level is independent of variations in power supply voltage conditions and temperature conditions.Type: ApplicationFiled: May 27, 2008Publication date: December 3, 2009Inventors: Huihao Xu, Joseph Natonio, James D. Rockrohr, Michael A. Sorna
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Publication number: 20090261890Abstract: An apparatus and method for a regulated voltage boost charge pump for an integrated circuit (IC) device. The charge pump generally includes a plurality of switching networks and a lift capacitor that are intermittently coupled to an output capacitor or to a regulating transistor, a differential error amplifier biasing a gate terminal of the transistor, and a controller configured to alternate states of switches in the switching networks in a pre-selected timing relationship with a clock signal of the IC device.Type: ApplicationFiled: April 16, 2008Publication date: October 22, 2009Inventors: John A. Fifield, Bradford Hunter, Todd M. Rasmus, Michael A. Sorna, Daniel W. Storaska