Abstract: The present invention provides a method to improve adhesion of barrier, metal, dielectric interfaces. In the process flow, a first barrier material is formed on a dielectric layer and bombarded with a plasma to effectively push the barrier material into the dielectric interface while leaving a portion of the barrier material over the dielectric. A second barrier material, which may or may not be the same as the first barrier material, is then formed on the remaining first barrier material. Advantageously, the method of the present invention allows the barrier material to be pushed into the dielectric to insure excellent adhesion, which prevents chemical mechanical polishing delamination. Furthermore, the presence of the first barrier material on the sidewalls of via apertures through the dielectric can prevent Cu poisoning from sputtered Cu or CxOy.

Abstract: Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The third operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage especially over the bottoms of unlanded vias. The forth operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In addition, techniques to protect the bottoms of the unlanded vias are described.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: A method of depositing thin films comprising Ti and TiN within vias and trenches having high aspect ratio openings. The Ti and TiN layers are formed on an integrated circuit substrate using a Ti target in a non-nitrided mode in a hollow cathode magnetron apparatus in combination with controlling the deposition temperatures by integrating cooling steps into the Ti/TiN deposition processes to modulate the via and contact resistance. The Ti and TiN layers are deposited within a single deposition chamber, without the use of a collimator or a shutter.

Abstract: A method of depositing thin films comprising Ti and TiN within vias and trenches having high aspect ratio openings of 6:1 is disclosed. The Ti and TiN layers are formed on an integrated circuit substrate using a Ti target in a non-nitrided mode in a hollow cathode magnetron apparatus in combination with an RF biased electrostatic chuck to modulate the properties of the deposited Ti and TiN layers in the same chamber, without the use of a collimator or a shutter. The resulting Ti and TiN layers are superior in step coverage, grain size, grain orientation, roughness and uniformity such that subsequent filling of the high aspect ratio opening is substantially void-free.

Abstract: The present invention pertains to methods for depositing a metal seed layer on a wafer substrate having a plurality of recessed features. Methods of the invention include at least two operations. A first portion of a seed layer is deposited such that metal ions impinge on the wafer substrate substantially perpendicular to the wafer substrate work surface. The first portion is characterized by heavy bottom coverage in the recessed features and minimal overhang on the apertures of the recessed features. A second portion of the metal seed layer is deposited with simultaneous re-sputter of at least part of the first portion that covers the bottom of the features. During re-sputter, part of the seed material on the bottom is redistributed to the sidewalls of the features. Seed layers of the invention have minimal overhang and excellent step coverage.

Abstract: The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.

Abstract: The present invention pertains to systems and methods for improving the deposition of conformal copper seed layers in integrated circuit metalization. The invention involves controlling the morphology of the barrier layer deposited underneath the copper seed layer. The barrier layer can be composed of TaN and Ta, or TaN alone. It can also be composed of TiN or TiNSi. The process conditions of the barrier layer deposition are carried out in a manner that results in a highly or completely amorphous crystalline structure. Such a barrier layer allows for conformal deposition of the copper seed layer on top of the barrier layer that is less susceptible to agglomeration.

Abstract: The present invention pertains to systems and methods for passivating the copper seed layer deposited in Damascene integrated circuit manufacturing. More specifically, the invention pertains to systems and methods for depositing the copper seed layer by physical vapor deposition, while passivating the copper during or immediately after the deposition in order to prevent excessive oxidation of the copper. The invention is applicable to dual Damascene processing.

Abstract: The present invention pertains to methods for forming diffusion barrier layers in the context of integrated circuit fabrication. Methods of the invention allow selective deposition of a metal-nitride barrier layer material on a partially fabricated integrated circuit having exposed conductor and dielectric regions and conversion of the metal-nitride barrier material into an effective diffusion barrier layer having low via resistance. In a preferred method using TiN, differential morphology in a single barrier layer deposition is achieved by controlling CVD process conditions. It is believed that the absolute amount of TiN deposited on the conductor is not reduced, but the morphology of is changed so that there is little or no increase in the via resistance after barrier formation. The invention also pertains to novel integrated circuit structures resulting from application of the described methods.

Abstract: Diffusion barriers are used in integrated circuits. The present method of depositing diffusion barriers eliminates the formation of high resistivity phases, providing high electrical conductivity and diffusion suppression between the interconnect conductors, for example copper, and the semiconductor device. In a preferred embodiment, the diffusion barrier is formed by depositing a film of binary transition metal nitride then treating the film in a gas containing silicon in order to form a layer of silicon rich material on the surface of the binary transition metal nitride film.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: A method of depositing titanium nitride by chemical vapor deposition in a chamber having several design features directed to the conductive nature of titanium nitride, particularly when a plasma treatment step is performed after the thermal deposition of the film. Preferably, during the post-deposition plasma treatment, RF power is applied only to the showerhead counter-electrode and none to the pedestal supporting the wafer, thereby preventing charging of the wafer.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: A method of depositing titanium nitride by chemical vapor deposition in a chamber having several design features directed to the conductive nature of titanium nitride, particularly when a plasma treatment step is performed after the thermal deposition of the film. Preferably, during the post-deposition plasma treatment, RF power is applied only to the showerhead counter-electrode and none to the pedestal supporting the wafer, thereby preventing charging of the wafer.

Abstract: The present invention provides an approach which provides an increase in the number of usable substrates with a film, such as titanium nitride, deposited thereon at a sufficient deposition rate and where the film meets uniformity and resistivity specifications as well as providing good step coverage. In accordance with an embodiment, the present invention provides an apparatus for substrate processing. The apparatus circulates a heat exchange medium through a passage in a chamber body of a vacuum chamber, and heats a heater pedestal having a surface for supporting the substrate to a heater temperature. The heat exchange medium has a heat exchange temperature of about 60.degree. C. or less. The the apparatus also flows a gas into the chamber at a flow rate to deposit a film on a substrate, where the flow rate provides an effective temperature of the substrate lower than the heater temperature and where the film meets uniformity and resistance specifications after deposition onto a number of substrates.