Patents by Inventor Michal Danek

Michal Danek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150325475
    Abstract: Methods for forming tungsten film using fluorine-free tungsten precursors such as tungsten chlorides are provided. Methods involve depositing a tungsten nucleation layer by exposing a substrate to a reducing agent such as diborane (B2H6) and exposing the substrate to a tungsten chloride, followed by depositing bulk tungsten by exposing the substrate to a tungsten chloride and a reducing agent. Methods also involve diluting the reducing agent and exposing the substrate to a fluorine-free precursor in pulses to deposit a tungsten nucleation layer. Deposited films exhibit good step coverage and plugfill.
    Type: Application
    Filed: May 4, 2015
    Publication date: November 12, 2015
    Inventors: Hanna Bamnolker, Raashina Humayun, Juwen Gao, Michal Danek, Joshua Collins
  • Patent number: 9159571
    Abstract: Methods for depositing low resistivity tungsten in features of substrates in semiconductor processing are disclosed herein. Methods involve using a germanium-containing reducing agent during tungsten nucleation layer deposition to achieve thin, low resistivity nucleation layers.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: October 13, 2015
    Assignee: Lam Research Corporation
    Inventors: Raashina Humayun, Sudha Manandhar, Michal Danek
  • Patent number: 9099535
    Abstract: The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: August 4, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Robert Rozbicki, Michal Danek, Erich Klawuhn
  • Patent number: 9034768
    Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials are provided. The method involves providing a partially fabricated semiconductor substrate and depositing a tungsten-containing layer on the substrate surface to partially fill one or more high aspect ratio features. The method continues with selective removal of a portion of the deposited layer such that more material is removed near the feature opening than inside the feature. In certain embodiments, removal may be performed at mass-transport limited conditions with less etchant available inside the feature than near its opening. Etchant species are activated before being introduced into the processing chamber and/or while inside the chamber. In specific embodiments, recombination of the activated species is substantially limited and/or controlled during removal, e.g., operation is performed at less than about 250° C. and/or less than about 5 Torr.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: May 19, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Raashina Humayun, Michal Danek, Aaron R. Fellis, Sean Chang
  • Patent number: 8975184
    Abstract: Methods of filling features with low-resistivity tungsten layers having good fill without use of a nucleation layer are provided. In certain embodiments, the methods involve an optional treatment process prior to chemical vapor deposition of tungsten in the presence of a high partial pressure of hydrogen. According to various embodiments, the treatment process can involve a soaking step or a plasma treatment step. The resulting tungsten layer reduces overall contact resistance in advanced tungsten technology due to elimination of the conventional tungsten nucleation layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Michal Danek
  • Publication number: 20150056803
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Application
    Filed: September 30, 2014
    Publication date: February 26, 2015
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20150037972
    Abstract: Described are cleaning methods for removing contaminants from an electrical contact interface of a partially fabricated semiconductor substrate. The methods may include introducing a halogen-containing species into a processing chamber, and forming an adsorption-limited layer, which includes halogen from the halogen-containing species, atop the electrical contact interface and/or the contaminants thereon. The methods may further include thereafter removing un-adsorbed halogen-containing species from the processing chamber and activating a reaction between the halogen of the adsorption-limited layer and the contaminants present on the electrical contact interface. The reaction may then result in the removal of at least a portion of the contaminants from the electrical contact interface. In some embodiments, the halogen adsorbed onto the surface and reacted may be fluorine. Also described herein are apparatuses having controllers for implementing such electrical contact interface cleaning techniques.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 5, 2015
    Inventors: Michal Danek, Juwen Gao, Aaron Fellis, Francisco Juarez, Chiukin Steven Lai
  • Patent number: 8883637
    Abstract: A method for filling a recessed feature of a substrate includes a) at least partially filling a recessed feature of a substrate with tungsten-containing film using at least one of chemical vapor deposition (CVD) and atomic layer deposition (ALD); b) at a predetermined temperature, using an etchant including activated fluorine species to selectively etch the tungsten-containing film more than an underlying material of the recessed feature without removing all of the tungsten-containing film at a bottom of the recessed feature; and c) filling the recessed feature using at least one of CVD and ALD.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: November 11, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Esther Jeng, Anand Chandrashekar, Raashina Humayun, Michal Danek, Ronald Powell
  • Patent number: 8835317
    Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: September 16, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Raashina Humayun, Michal Danek, Aaron R. Fellis, Sean Chang
  • Patent number: 8778797
    Abstract: A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 15, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Juwen Gao, Rajkumar Jakkaraju, Michal Danek, Wei Lei
  • Publication number: 20140162451
    Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 12, 2014
    Applicant: Novellus Systems, Inc.
    Inventors: Feng Chen, Raashina Humayun, Michal Danek, Anand Chandrashekar
  • Publication number: 20140154883
    Abstract: Methods for depositing low resistivity tungsten in features of substrates in semiconductor processing are disclosed herein. Methods involve using a germanium-containing reducing agent during tungsten nucleation layer deposition to achieve thin, low resistivity nucleation layers.
    Type: Application
    Filed: February 5, 2014
    Publication date: June 5, 2014
    Applicant: Lam Research Corporation
    Inventors: Raashina Humayun, Sudha Manandhar, Michal Danek
  • Publication number: 20140134827
    Abstract: A method and apparatus for conformally depositing a dielectric oxide in high aspect ratio gaps in a substrate is disclosed. A substrate is provided with one or more gaps into a reaction chamber where each gap has a depth to width aspect ratio of greater than about 5:1. A first dielectric oxide layer is deposited in the one or more gaps by CFD. A portion of the first dielectric oxide layer is etched using a plasma etch, where etching the portion of the first dielectric oxide layer occurs at a faster rate near a top surface than near a bottom surface of each gap so that the first dielectric oxide layer has a tapered profile from the top surface to the bottom surface of each gap. A second dielectric oxide layer is deposited in the one or more gaps over the first dielectric oxide layer via CFD.
    Type: Application
    Filed: November 7, 2013
    Publication date: May 15, 2014
    Applicant: Novellus Systems, Inc.
    Inventors: Shankar Swaminathan, Bart van Schravendijk, Adrien Lavoie, Sesha Varadarajan, Jason Daejin Park, Michal Danek, Naohiro Shoda
  • Patent number: 8709948
    Abstract: Apparatus and methods for filling through silicon vias (TSV's) with copper having an intervening tungsten layer between the copper plug and the silicon are disclosed. Methods are useful for Damascene processing, with or without a TSV feature. The tungsten layer serves as a diffusion barrier, a seed layer for copper electrofill and a means of reducing CTE-induced stresses between copper and silicon. Adhesion of the tungsten layer to the silicon and of the copper layer to the tungsten is described.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: April 29, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Michal Danek, Tom Mountsier, Jonathan Reid, Juwen Gao, Aaron Fellis
  • Patent number: 8685867
    Abstract: Provided herein are novel pre-metal dielectric (PMD) integration schemes. According to various embodiments, the methods involve depositing flowable dielectric material to fill trenches or other gaps between gate structures in a front end of line (FEOL) fabrication process. The flowable dielectric material may be partially densified to form dual density filled gaps having a low density region capped by a high density region. In certain embodiments, the methods include further treating at least a portion of the gap fill material after subsequent process operations such as chemical mechanical planarization (CMP) or contact etching.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: April 1, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Michal Danek, Bart van Schravendijk, Nerissa Draeger, Lakshminarayana Nittala
  • Patent number: 8679972
    Abstract: The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 25, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Robert Rozbicki, Michal Danek, Erich Klawuhn
  • Publication number: 20140030889
    Abstract: Methods of filling features with low-resistivity tungsten layers having good fill without use of a nucleation layer are provided. In certain embodiments, the methods involve an optional treatment process prior to chemical vapor deposition of tungsten in the presence of a high partial pressure of hydrogen. According to various embodiments, the treatment process can involve a soaking step or a plasma treatment step. The resulting tungsten layer reduces overall contact resistance in advanced tungsten technology due to elimination of the conventional tungsten nucleation layer.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Michal Danek
  • Patent number: 8623733
    Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: January 7, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Raashina Humayun, Michal Danek, Anand Chandrashekar
  • Patent number: 8617982
    Abstract: Certain embodiments pertain to local interconnects formed by subtractive patterning of blanket layer of tungsten or other conductive material. The grain sizes of tungsten or other deposited metal can be grown to relatively large dimensions, which results in increased electrical conductivity due to, e.g., reduced electron scattering at grain boundaries as electrons travel from one grain to the next during conduction.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: December 31, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Michal Danek, Juwen Gao, Ronald A. Powell, Aaron R. Fellis
  • Publication number: 20130330926
    Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.
    Type: Application
    Filed: May 6, 2013
    Publication date: December 12, 2013
    Inventors: Anand Chandrashekar, Raashina Humayun, Michal Danek, Aaron R. Fellis, Sean Chang