Patents by Inventor Michal Danek

Michal Danek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9502238
    Abstract: Methods for depositing conformal films using a halogen-containing etchant during atomic layer deposition are provided. Methods involve exposing a substrate to a halogen-containing etchant such as nitrogen trifluoride between exposing the substrate to a first precursor and exposing the substrate to a second plasma-activated reactant. Examples of conformal films that may be deposited include silicon-containing films and metal-containing films. Related apparatuses are also provided.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: November 22, 2016
    Assignee: Lam Research Corporation
    Inventors: Michal Danek, Jon Henri, Shane Tang
  • Patent number: 9478438
    Abstract: Methods of depositing highly conformal and pure titanium films at low temperatures are provided. Methods involve exposing a substrate to titanium tetraiodide, purging the chamber, exposing the substrate to a plasma, purging the chamber, and repeating these operations. Titanium films are deposited at low temperatures less than about 450° C.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: October 25, 2016
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Ishtak Karim, Sanjay Gopinath, Michal Danek
  • Patent number: 9478411
    Abstract: Methods of depositing and tuning deposition of sub-stoichiometric titanium oxide are provided. Methods involve depositing highly pure and conformal titanium on a substrate in a chamber by (i) exposing the substrate to titanium tetraiodide, (ii) purging the chamber, (iii) exposing the substrate to a plasma, (iv) purging the chamber, (v) repeating (i) through (iv), and treating the deposited titanium on the substrate to form sub-stoichiometric titanium oxide. Titanium oxide may also be deposited prior to depositing titanium on the substrate. Treatments include substrate exposure to an oxygen source and/or annealing the substrate.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: October 25, 2016
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Ishtak Karim, Sanjay Gopinath, Reza Arghavani, Michal Danek
  • Publication number: 20160293398
    Abstract: Methods for depositing conformal films using a halogen-containing etchant during atomic layer deposition are provided. Methods involve exposing a substrate to a halogen-containing etchant such as nitrogen trifluoride between exposing the substrate to a first precursor and exposing the substrate to a second plasma-activated reactant. Examples of conformal films that may be deposited include silicon-containing films and metal-containing films. Related apparatuses are also provided.
    Type: Application
    Filed: April 3, 2015
    Publication date: October 6, 2016
    Inventors: Michal Danek, Jon Henri, Shane Tang
  • Publication number: 20160233220
    Abstract: Disclosed herein are methods and related apparatus for formation of tungsten wordlines in memory devices. Also disclosed herein are methods and related apparatus for deposition of fluorine-free tungsten (FFW). According to various embodiments, the methods involve deposition of multi-component tungsten films using tungsten chloride (WClx) precursors and boron (B)-containing, silicon (Si)-containing or germanium (Ge)-containing reducing agents.
    Type: Application
    Filed: February 10, 2016
    Publication date: August 11, 2016
    Inventors: Michal Danek, Hanna Bamnolker, Raashina Humayun, Juwen Gao
  • Publication number: 20160190008
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Application
    Filed: December 10, 2015
    Publication date: June 30, 2016
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 9362163
    Abstract: Described are cleaning methods for removing contaminants from an electrical contact interface of a partially fabricated semiconductor substrate. The methods may include introducing a halogen-containing species into a processing chamber, and forming an adsorption-limited layer, which includes halogen from the halogen-containing species, atop the electrical contact interface and/or the contaminants thereon. The methods may further include thereafter removing un-adsorbed halogen-containing species from the processing chamber and activating a reaction between the halogen of the adsorption-limited layer and the contaminants present on the electrical contact interface. The reaction may then result in the removal of at least a portion of the contaminants from the electrical contact interface. In some embodiments, the halogen adsorbed onto the surface and reacted may be fluorine. Also described herein are apparatuses having controllers for implementing such electrical contact interface cleaning techniques.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: June 7, 2016
    Assignee: Lam Research Corporation
    Inventors: Michal Danek, Juwen Gao, Aaron Fellis, Francisco Juarez, Chiukin Steven Lai
  • Patent number: 9355886
    Abstract: A method and apparatus for conformally depositing a dielectric oxide in high aspect ratio gaps in a substrate is disclosed. A substrate is provided with one or more gaps into a reaction chamber where each gap has a depth to width aspect ratio of greater than about 5:1. A first dielectric oxide layer is deposited in the one or more gaps by CFD. A portion of the first dielectric oxide layer is etched using a plasma etch, where etching the portion of the first dielectric oxide layer occurs at a faster rate near a top surface than near a bottom surface of each gap so that the first dielectric oxide layer has a tapered profile from the top surface to the bottom surface of each gap. A second dielectric oxide layer is deposited in the one or more gaps over the first dielectric oxide layer via CFD.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: May 31, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Shankar Swaminathan, Bart van Schravendijk, Adrien LaVoie, Sesha Varadarajan, Jason Daejin Park, Michal Danek, Naohiro Shoda
  • Patent number: 9349637
    Abstract: Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt, (b) exposing the feature to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation on surfaces near or at the top of the feature, optionally repeating (a) and (b), and depositing bulk cobalt into the feature by chemical vapor deposition. Methods may also involve exposing a feature including a barrier layer to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation. The methods may be performed at low temperatures less than about 400° C. using cobalt-containing precursors.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 24, 2016
    Assignee: Lam Research Corporation
    Inventors: Jeong-Seok Na, Tianhua Yu, Michal Danek, Sanjay Gopinath
  • Publication number: 20160118345
    Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.
    Type: Application
    Filed: January 6, 2016
    Publication date: April 28, 2016
    Inventors: Feng Chen, Raashina Humayun, Michal Danek, Anand Chandrashekar
  • Publication number: 20160093528
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 31, 2016
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20160071764
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.
    Type: Application
    Filed: February 22, 2013
    Publication date: March 10, 2016
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20160056037
    Abstract: Methods of depositing and tuning deposition of sub-stoichiometric titanium oxide are provided. Methods involve depositing highly pure and conformal titanium on a substrate in a chamber by (i) exposing the substrate to titanium tetraiodide, (ii) purging the chamber, (iii) exposing the substrate to a plasma, (iv) purging the chamber, (v) repeating (i) through (iv), and treating the deposited titanium on the substrate to form sub-stoichiometric titanium oxide. Titanium oxide may also be deposited prior to depositing titanium on the substrate. Treatments include substrate exposure to an oxygen source and/or annealing the substrate.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 25, 2016
    Inventors: Shruti Vivek Thombare, Ishtak Karim, Sanjay Gopinath, Reza Arghavani, Michal Danek
  • Publication number: 20160056077
    Abstract: Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt, (b) exposing the feature to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation on surfaces near or at the top of the feature, optionally repeating (a) and (b), and depositing bulk cobalt into the feature by chemical vapor deposition. Methods may also involve exposing a feature including a barrier layer to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation. The methods may be performed at low temperatures less than about 400° C. using cobalt-containing precursors. Methods may also involve using a remote plasma source to generate the nitrogen-based plasma. Methods also involve annealing the substrate.
    Type: Application
    Filed: October 1, 2015
    Publication date: February 25, 2016
    Inventors: Chiukin Steven Lai, Jeong-Seok Na, Raihan Tarafdar, Raashina Humayun, Michal Danek
  • Publication number: 20160056053
    Abstract: Methods of depositing highly conformal and pure titanium films at low temperatures are provided. Methods involve exposing a substrate to titanium tetraiodide, purging the chamber, exposing the substrate to a plasma, purging the chamber, and repeating these operations. Titanium films are deposited at low temperatures less than about 450° C.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 25, 2016
    Inventors: Shruti Vivek Thombare, Ishtak Karim, Sanjay Gopinath, Michal Danek
  • Publication number: 20160056074
    Abstract: Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt, (b) exposing the feature to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation on surfaces near or at the top of the feature, optionally repeating (a) and (b), and depositing bulk cobalt into the feature by chemical vapor deposition. Methods may also involve exposing a feature including a barrier layer to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation. The methods may be performed at low temperatures less than about 400° C. using cobalt-containing precursors.
    Type: Application
    Filed: August 21, 2014
    Publication date: February 25, 2016
    Inventors: Jeong-Seok Na, Tianhua Yu, Michal Danek, Sanjay Gopinath
  • Patent number: 9257302
    Abstract: Provided are methods of filling gaps on a substrate by creating flowable silicon oxide-containing films. The methods involve introducing vapor-phase silicon-containing precursor and oxidant reactants into a reaction chamber containing the substrate under conditions such that a condensed flowable film is formed on the substrate. The flowable film at least partially fills gaps on the substrate. In certain embodiments, the methods involve using a catalyst in the formation of the film. The catalyst may be incorporated into one of the reactants and/or introduced as a separate reactant.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: February 9, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Wang, Brian Lu, Nerissa Draeger, Vishal Gauri, Raashina Humayun, Michal Danek, Bart van Schravendijk, Lakshminarayana Nittala
  • Patent number: 9240347
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 19, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 9236297
    Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: January 12, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Raashina Humayun, Michal Danek, Anand Chandrashekar
  • Publication number: 20150348840
    Abstract: Provided herein are methods and apparatus for depositing and etching tungsten. The methods involve using tungsten chlorides (WClx) as both precursor and etchant. In some embodiments, the exposing the substrate to a WClx precursor and a reducing agent at a first set of conditions to deposit a first tungsten layer in a feature on a substrate; and exposing the substrate to a WClx precursor and a reducing agent at a second set of conditions to etch the first tungsten layer. According to various embodiments, transitioning from a deposition to etch regime can involve one or more of increasing a WClx flux, decreasing a temperature, and changing the WClx precursor. Also provided are related apparatus.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 3, 2015
    Inventors: Hanna Bamnolker, Raashina Humayun, Michal Danek, Joshua Collins