Patents by Inventor Michele Piccardi

Michele Piccardi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942164
    Abstract: Devices and techniques are disclosed herein to provide a number of different bias signals to each of multiple signal lines of an array of memory cells, each bias signal having an overdrive voltage above a target voltage by a selected increment and an overdrive period, to determine settling times of each of the multiple signal lines to the target voltage for the number of different bias signals, to determine a functional compensation profile for an array of memory cells comprising a relationship between the different bias signals and the determined settling times of the multiple signal lines.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Luyen Tien Vu
  • Patent number: 11881282
    Abstract: A memory device including a memory die including an internally-powered thermometer to determine a first measured operating temperature value of the memory die; detect the first measured operating temperature value satisfies one of a first condition or a second condition; and generate a first signal indicating an out-of-range operating temperature of the memory die in response to one of the first condition or the second condition being satisfied by the first measured operating temperature value. The memory die also including an externally-powered thermometer to: determine a second measured operating temperature value of the memory die; detect the second measured operating temperature value satisfies one of the first condition or the second condition; and generate a second signal indicating the out-of-range operating temperature of the memory die in response to one of the first condition or the second condition being satisfied by the second measured operating temperature value.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: January 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yui Shimizu, Manik Advani, Michele Piccardi
  • Patent number: 11869603
    Abstract: Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Shuai Xu, Michele Piccardi, June Lee
  • Publication number: 20230317120
    Abstract: A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.
    Type: Application
    Filed: December 22, 2020
    Publication date: October 5, 2023
    Inventors: Shuai Xu, Michele Piccardi, Arvind Muralidharan, June Lee, Qisong Lin, Scott A. Stoller, Jun Shen
  • Patent number: 11763858
    Abstract: A system includes a charge pump to charge wordlines of a memory array, a pump regulator coupled including a level detector, and dynamic clock logic coupled between the level detector and an oscillator. The logic provides clock signals to the charge pump and is to perform operations including causing the oscillator to output, to the charge pump during a first time period of a recovery period of the charge pump, a first clock signal having a lower frequency than output during a time period preceding the recovery period. The operations further include causing the oscillator to output, to the charge pump during a second time period of the recovery period that follows the first time period, a second clock signal having a higher frequency than output during the time period preceding the recovery period.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Vivek Venkata Kalluru, Michele Piccardi
  • Patent number: 11763895
    Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Qisong Lin, Shuai Xu, Jonathan S. Parry, Jeremy Binfet, Michele Piccardi, Qing Liang
  • Patent number: 11710533
    Abstract: A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: July 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Xiaojiang Guo, Jung Sheng Hoei, Michele Piccardi, Manan Tripathi
  • Patent number: 11704047
    Abstract: A system includes a memory array, a thermometer, and control logic, operatively coupled with the memory array and the thermometer, to perform operations including causing the thermometer to obtain a first temperature result, monitoring a time since obtaining the first temperature result, determining whether the time satisfies a threshold time condition, in response to determining that the time satisfies the threshold time condition, causing the thermometer to obtain a second temperature result from an automatic temperature reading, determining a difference between the second temperature result and a previously stored temperature result, and filtering the second temperature result based on the difference to obtain a new stored temperature result.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Macerola, Michele Piccardi, Umberto Siciliani, Tommaso Vali, Enrico Favaro
  • Patent number: 11688468
    Abstract: Devices and techniques are disclosed herein to provide a high-voltage bias signal in a standby state of the storage system without exceeding a limited maximum standby current allowance of the storage system. The high-voltage bias signal can enable a string driver circuit in the standby state to couple a global word line to a local word line, to provide a bias to, or sink a voltage from, a pillar of a string of memory cells of the storage system in the standby state, such as to reduce read disturbances in the storage system.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo, Shigekazu Yamada
  • Patent number: 11670346
    Abstract: Memory having an array of memory cells and a plurality of access lines each connected to a respective plurality of memory cells of the array of memory cells might include a controller configured to cause the memory to apply a respective programming pulse having a first target voltage level and a first pulse width to each access line of a first subset of access lines of the plurality of access lines, and apply a respective programming pulse having the first target voltage level and a second pulse width longer than the first pulse width to each access line of a second subset of access lines of the plurality of access lines, wherein each access line of the first subset of access lines is nearer a particular end of the string of series-connected memory cells than each access line of the second subset of access lines.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Chang H. Siau, Michele Piccardi, Qui V. Nguyen
  • Patent number: 11652409
    Abstract: Apparatus, systems, and methods are disclosed, including a high-voltage charge pump including multiple pump stages connected in series to provide a high-voltage output, a common discharge circuit, and multiple high-voltage devices coupled between the outputs of each of the multiple pump stages and the common discharge circuit. Each of the multiple pump stages include a low-voltage switching device. The common discharge circuit is coupled to each of the multiple pump stages and is configured to discharge the multiple pump stages when the multiple pump stages are disabled. The multiple high-voltage devices include a respective high-voltage device coupled between an output of each of the multiple pump stages and the common discharge circuit.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo
  • Patent number: 11631319
    Abstract: A resistor-capacitor (RC) sensor circuit includes an integration capacitor configured to integrate a representative copy of a current that drives an electronic circuit line. The integration capacitor is configured to integrate over a first time period to generate a first representative voltage and over a second time period to generate a second representative voltage. The RC sensor circuit includes a sampling circuit coupled to the integration capacitor and configured to sample the first representative voltage and the second representative voltage. A ratio of the first sampled voltage and the second sampled voltage is indicative of an RC time constant of the electronic circuit line.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: April 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Pin-Chou Chiang, Michele Piccardi, Theodore T. Pekny
  • Publication number: 20230116024
    Abstract: A first digitally-controlled pump voltage level is established for a charge pump coupled to a wordline of a memory device of a memory sub-system. A determination is made whether a measured digitally-controlled voltage level of the wordline and the first digitally-controlled pump voltage level satisfy a condition. In response to determining that the condition is satisfied, a signal is generated to adjust the first digitally-controlled pump voltage level to a second digitally-controlled pump voltage level.
    Type: Application
    Filed: September 2, 2022
    Publication date: April 13, 2023
    Inventor: Michele Piccardi
  • Patent number: 11615853
    Abstract: A circuit includes a linear regulator coupled with a memory array and a pump regulator coupled with a charge pump, the charge pump to provide a supply voltage to the linear regulator. A digital-to-analog converter (DAC) has an output coupled with the pump regulator. Control logic is coupled with the DAC and is to perform operations including causing a digital input value to be provided to the DAC to selectively adjust the supply voltage based on a programmable offset value.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: March 28, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Publication number: 20230063585
    Abstract: A memory device including a memory die including an internally-powered thermometer to determine a first measured operating temperature value of the memory die; detect the first measured operating temperature value satisfies one of a first condition or a second condition; and generate a first signal indicating an out-of-range operating temperature of the memory die in response to one of the first condition or the second condition being satisfied by the first measured operating temperature value. The memory die also including an externally-powered thermometer to: determine a second measured operating temperature value of the memory die; detect the second measured operating temperature value satisfies one of the first condition or the second condition; and generate a second signal indicating the out-of-range operating temperature of the memory die in response to one of the first condition or the second condition being satisfied by the second measured operating temperature value.
    Type: Application
    Filed: March 7, 2022
    Publication date: March 2, 2023
    Inventors: Yui Shimizu, Manik Advani, Michele Piccardi
  • Publication number: 20230059543
    Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 23, 2023
    Inventors: Andrea Giovanni Xotta, Dheeraj Srinivasan, Ali Mohammadzadeh, Karl D. Schuh, Guido Luciano Rizzo, Jung Sheng Hoei, Michele Piccardi, Tommaso Vali, Umberto Siciliani, Rohitkumar Makhija, June Lee, Aaron S. Yip, Daniel J. Hubbard
  • Publication number: 20230057289
    Abstract: Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.
    Type: Application
    Filed: February 10, 2022
    Publication date: February 23, 2023
    Inventors: Vivek Venkata Kalluru, Michele Piccardi, Taehyun Kim, Theodore T. Pekny
  • Publication number: 20230047662
    Abstract: A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 16, 2023
    Inventors: Erwin E. Yu, Michele Piccardi, Surendranath C. Eruvuru
  • Publication number: 20230046421
    Abstract: Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 16, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shuai Xu, Michele Piccardi, June Lee
  • Patent number: 11573588
    Abstract: Apparatus and methods are disclosed for providing a bias, comprising a bias generator circuit including a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line and a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: February 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo