Abstract: Devices and techniques are disclosed herein to provide a high-voltage bias signal in a standby state of the storage system without exceeding a limited maximum standby current allowance of the storage system. The high-voltage bias signal can enable a string driver circuit in the standby state to couple a global word line to a local word line, to provide a bias to, or sink a voltage from, a pillar of a string of memory cells of the storage system in the standby state, such as to reduce read disturbances in the storage system.

Abstract: An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster includes: a controller capacitor configured to store energy for providing a control signal, wherein the control signal is for controlling charging operations to generate the boosted intermediate voltage based on the source voltage, and a booster capacitor configured to store energy according to the control signal for providing the boosted intermediate voltage; and a secondary booster operatively coupled to the clock booster, the secondary booster configured to generate an output voltage based on the boosted intermediate voltage, wherein the output voltage is greater than both the source voltage and the boosted intermediate voltage.

Abstract: The RC sensor circuit includes a driver circuit that includes an output configured to drive the RC sensor circuit to a drive voltage using a representative copy of a current that drives an electronic circuit line. The RC sensor circuit includes an integration capacitor. The integration capacitor is configured to integrate the representative copy of the current over a first time period to generate a first representative voltage and over a second time period to generate a second representative voltage. The RC sensor circuit includes a sampling circuit coupled to the integration capacitor. The sampling circuit is configured to determine a first sample voltage by sampling the first representative voltage and a second sample voltage by sampling the second representative voltage. A ratio of the first sample voltage and the second sample voltage is indicative of an RC time constant of the electronic circuit line.

Abstract: Disclosed are systems and methods of dynamically calibrating a memory control voltage more accurately. According to disclosed implementations, a memory control voltage such as Vpass or Vwlrv may be calibrated during memory operation as a function of the change in slope of total string current, even during increase in the wordline voltage. In one exemplary method, the wordlines are increased in sequence from a start voltage to an end voltage in steps, slope change is measured at every step, the measured slope change is compared against a threshold, and an adjusted memory control voltage is determined as a function of a wordline voltage at which the change in slope reaches the threshold. As such, memory control voltage may be determined and dynamically calibrated with less sensitivity to operating parameters such as temperature, pattern, and/or time of programming.

Abstract: A resistor-capacitor (RC) sensor circuit of an electronic device is driven to a drive voltage using a representative copy of a current that drives an electronic circuit line of the electronic device. The RC sensor circuit is to sample voltages that are indicative of an RC time constant of the electronic circuit line. A first sample voltage is determined by sampling a first representative voltage generated at the RC sensor circuit by driving the RC sensor circuit with the representative copy of the current over a first time period. A second sample voltage is determined by sampling a second representative voltage generated at the RC sensor circuit by driving the RC sensor circuit with the representative copy of the current over a second time period. A ratio of the first sample voltage and the second sample voltage is indicative of the RC time constant of the electronic circuit line.

Abstract: The RC sensor circuit includes a driver circuit that includes an output configured to drive the RC sensor circuit to a drive voltage using a representative copy of a current that drives an electronic circuit line. The RC sensor circuit includes an integration capacitor. The integration capacitor is configured to integrate the representative copy of the current over a first time period to generate a first representative voltage and over a second time period to generate a second representative voltage. The RC sensor circuit includes a sampling circuit coupled to the integration capacitor. The sampling circuit is configured to determine a first sample voltage by sampling the first representative voltage and a second sample voltage by sampling the second representative voltage. A ratio of the first sample voltage and the second sample voltage is indicative of an RC time constant of the electronic circuit line.

Abstract: A voltage generation system might include a selectively-enabled resistive voltage divider having a first resistor connected between an output of the voltage generation system and a first feedback node and having a second resistor connected between the first feedback node and a first voltage node; a selectively-enabled capacitive voltage divider having a first capacitor connected between the output and a second feedback node and having a second capacitor connected between the second feedback node and the first voltage node; a comparator having a first input connected to the second feedback node, having a second input connected to a control signal node, and having an output; and a voltage generation circuit configured to generate a voltage level at the output responsive to a logic level of the output of the comparator and to a clock signal; wherein the first feedback node is selectively connected to the second feedback node.

Abstract: A memory device includes a memory array comprising a plurality of planes, a plurality of voltage generation systems, and a controller. Each voltage generation system of the plurality of voltage generation systems is electrically coupled to a corresponding plane of the plurality of planes. The controller is configured to turn on each voltage generation system of the plurality of voltage generation systems in response to a first command to access a first plane of the plurality of planes. The controller is configured to operate the voltage generation system of the plurality of voltage generation systems corresponding to the first plane of the plurality of planes at a first clock frequency, and operate the remaining voltage generation systems of the plurality of voltage generation systems corresponding to the other planes of the plurality of planes at a second clock frequency less than the first clock frequency.

Abstract: An electronic device comprises a multi-chip package including multiple memory dice that include a memory array, charging circuitry, polling circuitry and a control unit. The charging circuitry is configured to perform one or more memory events in a high current mode using a high current level or in a low current mode using a lower current level. The polling circuitry is configured to poll a power status node common to the multiple memory dice to determine availability of the high current mode. The control unit is configured to operate the charging circuitry in the high current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is available, and operate the charging circuitry in the low current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is unavailable.

Abstract: Integrated circuit devices might include a controller configured to cause the integrated circuit device to apply a first voltage level to a first conductor while applying a second voltage level to a second conductor, apply a third voltage level to the first conductor while applying a fourth voltage level to the second conductor, and apply a fifth voltage level to the first conductor while applying the second voltage level to the second conductor. The second voltage level might correspond to a target voltage level for the second conductor. A difference between the third voltage level and the first voltage level might have a polarity opposite the polarity of a difference between the fourth voltage level and the second voltage level, and the same polarity of a difference between the fifth voltage level and the first voltage level. The fifth voltage level might correspond to a target voltage level for the first conductor.

Abstract: Disclosed are systems and methods of dynamically calibrating a memory control voltage more accurately. According to disclosed implementations, a memory control voltage such as Vpass or Vwlrv may be calibrated during memory operation as a function of the change in slope of total string current, even during increase in the wordline voltage. In one exemplary method, the wordlines are increased in sequence from a start voltage to an end voltage in steps, slope change is measured at every step, the measured slope change is compared against a threshold, and an adjusted memory control voltage is determined as a function of a wordline voltage at which the change in slope reaches the threshold. As such, memory control voltage may be determined and dynamically calibrated with less sensitivity to operating parameters such as temperature, pattern, and/or time of programming.

Abstract: Devices and techniques are disclosed herein to compensate for variance in one or more electrical parameters across multiple signal lines of an array of memory cells. A compensation circuit can provide a bias signal to a first one of the multiple signal lines, the bias signal having an overdrive voltage greater than a target voltage by a selected increment for a selected overdrive period.

Abstract: Memories having an array of memory cells might include a plurality of voltage generation systems each having a respective output selectively connected to a respective access line, and a voltage regulator having an input connected to the output of each of the voltage generation systems, and having an output selectively connected to the respective access line for each of the voltage generation systems.

Abstract: Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the charge pump, and a charge pump regulator circuit coupled to the charge pump. One such charge pump regulator circuit is configured to control the charge pump to increase the output voltage during a first period of time. Such a charge pump regulator circuit can also cause a node of a circuit coupled to the output node of the charge pump to reach a target voltage level during a second time period.

Abstract: Systems and methods of dynamically calibrating memory control signals during increase of wordline voltage for memory technologies subject to charge loss are disclosed. In one aspect, an exemplary method may comprise using an internal node, such as a wordline regulator output or return feedback line or a replica of the wordline, as proxy for the local wordline voltage. In one or more further embodiments, the proxy signal may be converted to digital signal or code and even determined in the background before the signal is needed for calibration. As a function of the disclosed technology, calibration of memory control signals, such as pass voltage and wordline read-verify voltage, may be performed during increase of the wordlines voltage with no impact or penalty on read/program time.

Abstract: Apparatus, systems, and methods are disclosed, including a high-voltage charge pump including multiple pump stages connected in series to provide a high-voltage output, a common discharge circuit, and multiple high-voltage devices coupled between the outputs of each of the multiple pump stages and the common discharge circuit. Each of the multiple pump stages include a low-voltage switching device. The common discharge circuit is coupled to each of the multiple pump stages and is configured to discharge the multiple pump stages when the multiple pump stages are disabled. The multiple high-voltage devices include a respective high-voltage device coupled between an output of each of the multiple pump stages and the common discharge circuit.

Abstract: An electronic device comprises a multi-chip package including multiple memory dice that include a memory array, charging circuitry, polling circuitry and a control unit. The charging circuitry is configured to perform one or more memory events in a high current mode using a high current level or in a low current mode using a lower current level. The polling circuitry is configured to poll a power status node common to the multiple memory dice to determine availability of the high current mode. The control unit is configured to operate the charging circuitry in the high current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is available, and operate the charging circuitry in the low current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is unavailable.

Abstract: Method of operating an integrated circuit device might include applying a first voltage level to a first conductor while applying a second voltage level to a second conductor, applying a third voltage level to the first conductor while applying a fourth voltage level to the second conductor, and applying a fifth voltage level to the first conductor while applying the second voltage level to the second conductor. The second voltage level might correspond to a target voltage level for the second conductor. A difference between the third voltage level and the first voltage level might have a polarity opposite the polarity of a difference between the fourth voltage level and the second voltage level, and the same polarity of a difference between the fifth voltage level and the first voltage level. The fifth voltage level might correspond to a target voltage level for the first conductor.

Abstract: Apparatus and methods are disclosed for providing a bias, comprising a bias generator circuit including a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line and a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line, wherein the LV circuit is configured to direct current used to generate the LV differential into the HV regulated line.

Abstract: An electronic device includes a reconfigurable charge pump including selectively connectable pump units for varying a generated voltage level. A control circuit may is configured to activate or deactivate the reconfigurable charge pump. The reconfigurable charge pump may track a duration based on activating the reconfigurable charge pump. When the duration exceeds a threshold, the control circuit may generates a signal according to the generated voltage level to reconfigure the electrical connections between the selectively connectable pump units.