Abstract: A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to the program voltage target; a sensor circuit that compares a duty cycle of the control signal to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.

Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

Abstract: Integrated circuit devices might include a controller configured to cause the integrated circuit device to apply a first voltage level to a first conductor while applying a second voltage level to a second conductor, apply a third voltage level to the first conductor while applying a fourth voltage level to the second conductor, and apply a fifth voltage level to the first conductor while applying the second voltage level to the second conductor. The second voltage level might correspond to a target voltage level for the second conductor. A difference between the third voltage level and the first voltage level might have a polarity opposite the polarity of a difference between the fourth voltage level and the second voltage level, and the same polarity of a difference between the fifth voltage level and the first voltage level. The fifth voltage level might correspond to a target voltage level for the first conductor.

Abstract: Apparatus, systems, and methods are disclosed, including a high-voltage charge pump including multiple pump stages connected in series to provide a high-voltage output, a common discharge circuit, and multiple high-voltage devices coupled between the outputs of each of the multiple pump stages and the common discharge circuit. Each of the multiple pump stages include a low-voltage switching device. The common discharge circuit is coupled to each of the multiple pump stages and is configured to discharge the multiple pump stages when the multiple pump stages are disabled. The multiple high-voltage devices include a respective high-voltage device coupled between an output of each of the multiple pump stages and the common discharge circuit.

Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

Abstract: A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.

Abstract: A circuit includes a linear regulator operatively coupled with a memory array, the linear regulator including a primary switch to generate a regulated voltage usable to program memory cells of the memory array. A first digital-to-analog converter (DAC) includes an output coupled with the linear regulator. A pump regulator is operatively coupled with a charge pump, where the charge pump is to provide a supply voltage to the linear regulator. A second DAC includes an output coupled with the pump regulator. Control logic, operatively coupled with the first DAC and the second DAC, is to perform operations including: causing a first digital input value to be provided to the first DAC to selectively smooth noise on the supply voltage; and causing a second digital input value to be provided the second DAC to selectively adjust the supply voltage based on a programmable offset value.

Abstract: Apparatus and methods are disclosed for providing a bias, comprising a bias generator circuit including a high voltage (HV) circuit configured to generate a regulated high voltage (HV) from an HV line and provide the regulated HV at an HV regulated line and a low voltage (LV) circuit configured to generate a low voltage (LV) differential from the HV line and to provide the LV differential at an LV line.

Abstract: A circuit includes a linear regulator operatively coupled with a memory array, the linear regulator including a primary switch to generate a regulated voltage usable to program memory cells of the memory array. A first digital-to-analog converter (DAC) includes an output coupled with the linear regulator. A pump regulator is operatively coupled with a charge pump, where the charge pump is to provide a supply voltage to the linear regulator. A second DAC includes an output coupled with the pump regulator. Control logic, operatively coupled with the first DAC and the second DAC, is to perform operations including: causing a first digital input value to be provided to the first DAC to selectively smooth noise on the supply voltage; and causing a second digital input value to be provided the second DAC to selectively adjust the supply voltage based on a programmable offset value.

Abstract: A first digitally-controlled pump voltage level is established for a charge pump coupled to a wordline of a memory device of a memory sub-system. A determination is made whether a measured digitally-controlled voltage level of the wordline and the first digitally-controlled pump voltage level satisfy a condition. In response to determining that the condition is satisfied, the first digitally-controlled pump voltage level applied to the charge pump is caused to change to a second digitally-controlled pump voltage level.

Abstract: Memories having an array of memory cells might include a plurality of voltage generation systems each having a respective output selectively connected to a respective access line, and a voltage regulator having an input connected to the output of each of the voltage generation systems, and having an output selectively connected to the respective access line for each of the voltage generation systems.

Abstract: Apparatus, systems, and methods are disclosed, including a high-voltage charge pump including multiple pump stages connected in series to provide a high-voltage output, a common discharge circuit, and multiple high-voltage devices coupled between the outputs of each of the multiple pump stages and the common discharge circuit. Each of the multiple pump stages include a low-voltage switching device. The common discharge circuit is coupled to each of the multiple pump stages and is configured to discharge the multiple pump stages when the multiple pump stages are disabled. The multiple high-voltage devices include a respective high-voltage device coupled between an output of each of the multiple pump stages and the common discharge circuit.

Abstract: A memory device includes a memory array comprising a plurality of planes, a plurality of voltage generation systems, and a controller. Each voltage generation system is electrically coupled to a corresponding plane. The controller is configured to turn on and warm up each voltage generation system of the plurality of voltage generation systems in response to a first command to access any plane of the plurality of planes and turn off and slowly discharge each voltage generation system of the plurality of voltage generation systems into an idle state in response to no commands being processed. In response to receiving a subsequent command to access any plane of the plurality of planes prior to the voltage generation systems reaching the idle state, a warm up period of the plurality of voltage generation systems is reduced.

Abstract: Disclosed are systems and methods of dynamically calibrating a memory control voltage more accurately. According to disclosed implementations, a memory control voltage such as Vpass or Vwlrv may be calibrated during memory operation as a function of the change in slope of total string current, even during increase in the wordline voltage. In one exemplary method, the wordlines are increased in sequence from a start voltage to an end voltage in steps, slope change is measured at every step, the measured slope change is compared against a threshold, and an adjusted memory control voltage is determined as a function of a wordline voltage at which the change in slope reaches the threshold. As such, memory control voltage may be determined and dynamically calibrated with less sensitivity to operating parameters such as temperature, pattern, and/or time of programming.

Abstract: A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.

Abstract: A system and a memory device including a driver circuit, to perform first operations including driving a resistor-capacitor (RC) sensor circuit of an electronic device to a drive voltage using a representative copy of a current that drives an electronic circuit line of the electronic device. The system and memory device including the RC sensor circuit, coupled to the driver circuit, to perform second operations including determining a first sample voltage by sampling a first representative voltage generated at the RC sensor circuit, and determining a second sample voltage by sampling a second representative voltage generated at the RC sensor circuit. The ratio of the first sample voltage and the second sample voltage is indicative of an RC time constant of the electronic circuit line.

Abstract: A voltage generation system might include a selectively-enabled resistive voltage divider having a first resistor connected between an output of the voltage generation system and a first feedback node and having a second resistor connected between the first feedback node and a first voltage node; a selectively-enabled capacitive voltage divider having a first capacitor connected between the output and a second feedback node and having a second capacitor connected between the second feedback node and the first voltage node; a comparator having a first input connected to the second feedback node, having a second input connected to a control signal node, and having an output; and a voltage generation circuit configured to generate a voltage level at the output responsive to a logic level of the output of the comparator and to a clock signal; wherein the first feedback node is selectively connected to the second feedback node.

Abstract: A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSSs) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.

Abstract: Memory having an array of memory cells and a plurality of access lines each connected to a respective plurality of memory cells of the array of memory cells might include a controller configured to cause the memory to apply a respective programming pulse having a first target voltage level and a first pulse width to each access line of a first subset of access lines of the plurality of access lines, and apply a respective programming pulse having the first target voltage level and a second pulse width longer than the first pulse width to each access line of a second subset of access lines of the plurality of access lines, wherein each access line of the first subset of access lines is nearer a particular end of the string of series-connected memory cells than each access line of the second subset of access lines.

Abstract: Devices and techniques are disclosed herein to provide a number of different bias signals to each of multiple signal lines of an array of memory cells, each bias signal having an overdrive voltage above a target voltage by a selected increment and an overdrive period, to determine settling times of each of the multiple signal lines to the target voltage for the number of different bias signals, to determine a functional compensation profile for an array of memory cells comprising a relationship between the different bias signals and the determined settling times of the multiple signal lines.