Abstract: An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor and provide a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use the voltage stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a direct charging duration for charging the booster capacitor using source-secondary current from an input voltage supply instead of or in addition to the voltage stored on the doubler capacitor.

Abstract: An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor and provide a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use the voltage stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a direct charging duration for charging the booster capacitor using source-secondary current from an input voltage supply instead of or in addition to the voltage stored on the doubler capacitor.

Abstract: An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor to store a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use charges stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a recycling duration for discharging a recycled charge from the booster capacitor to the doubler capacitor through the connecting switch, wherein the recycling duration is after generating the stage output.

Abstract: An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor and provide a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use the voltage stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a direct charging duration for charging the booster capacitor using source-secondary current from an input voltage supply instead of or in addition to the voltage stored on the doubler capacitor.

Abstract: An electronic device includes a reconfigurable charge pump including pump units that can be arranged differently for varying an output voltage generated by the reconfigurable charge pump; a pump regulator coupled to the reconfigurable charge pump, the pump regulator configured to monitor the output voltage and turn the reconfigurable charge pump on or off based on the output voltage; and an arrangement control mechanism coupled to the pump regulator, the arrangement control mechanism configured to control operation of the pump regulator based on the output voltage to generate arrangement control output, wherein the arrangement control output controls electrical connections between the pump units.

Abstract: An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster includes: a controller capacitor configured to store energy for providing a gate signal, wherein the gate signal is for controlling charging operations to generate the boosted intermediate voltage based on the source voltage, and a booster capacitor configured to store energy according to the gate signal for providing the boosted intermediate voltage, wherein the booster capacitor has greater capacitance level than the controller capacitor; and a secondary booster operatively coupled to the clock booster, the secondary booster configured to generate an output voltage based on the boosted intermediate voltage, wherein the output voltage is greater than both the source voltage and the boosted intermediate voltage.

Abstract: An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor and provide a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use the voltage stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a direct charging duration for charging the booster capacitor using source-secondary current from an input voltage supply instead of or in addition to the voltage stored on the doubler capacitor.

Abstract: Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the charge pump, and a charge pump regulator circuit coupled to the charge pump. One such charge pump regulator circuit is configured to control the charge pump to increase the output voltage during a first period of time. Such a charge pump regulator circuit can also cause a node of a circuit coupled to the output node of the charge pump to reach a target voltage level during a second time period.

Abstract: An electronic device includes a reconfigurable charge pump including pump units that can be arranged differently for varying an output voltage generated by the reconfigurable charge pump; a pump regulator coupled to the reconfigurable charge pump, the pump regulator configured to monitor the output voltage and turn the reconfigurable charge pump on or off based on the output voltage; and an arrangement control mechanism coupled to the pump regulator, the arrangement control mechanism configured to control operation of the pump regulator based on the output voltage to generate arrangement control output, wherein the arrangement control output controls electrical connections between the pump units.

Abstract: Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the charge pump, and a charge pump regulator circuit coupled to the charge pump. One such charge pump regulator circuit is configured to control the charge pump to increase the output voltage during a first period of time. Such a charge pump regulator circuit can also cause a node of a circuit coupled to the output node of the charge pump to reach a target voltage level during a second time period.

Abstract: Sense circuits, memory devices, and related methods are disclosed. A sense circuit includes sample and hold circuitry configured to sample and hold a second response voltage potential, a first response voltage potential, and a third response voltage potential responsive to an evaluation signal applied to a resistance variable memory cell. The sense circuit includes an amplifier operably coupled to the sample and hold circuitry. The amplifier is configured to amplify a difference between a sum of the first response voltage potential and the third response voltage potential, and twice the second response voltage potential. A memory device includes an evaluation signal generating circuit configured to provide the evaluation signal, an array of resistance variable memory cells, and the sense circuit. A method includes applying the evaluation signal to the resistance variable memory cell, sampling and holding the response voltage potentials, and discharging the sample and hold circuitry to the amplifier.

Abstract: Systems, apparatuses and methods may provide for determining a magnitude of a bounce voltage on a source line associated with one or more memory cells and conducting, if the magnitude of the bounce voltage exceeds a threshold, a coarse-level program verification and a fine-level program verification of the one or more memory cells. Additionally, if the magnitude of the bounce voltage does not exceed the threshold, only the fine-level program verification of the one or more memory cells may be conducted. In one example, the coarse-level program verification is bypassed if the magnitude of the bounce voltage does not exceed the threshold.

Abstract: Systems, apparatuses and methods may provide for determining a magnitude of a bounce voltage on a source line associated with one or more memory cells and conducting, if the magnitude of the bounce voltage exceeds a threshold, a coarse-level program verification and a fine-level program verification of the one or more memory cells. Additionally, if the magnitude of the bounce voltage does not exceed the threshold, only the fine-level program verification of the one or more memory cells may be conducted. In one example, the coarse-level program verification is bypassed if the magnitude of the bounce voltage does not exceed the threshold.

Abstract: Sense circuits, memory devices, and related methods are disclosed. A sense circuit includes sample and hold circuitry configured to sample and hold a second response voltage potential, a first response voltage potential, and a third response voltage potential responsive to an evaluation signal applied to a resistance variable memory cell. The sense circuit includes an amplifier operably coupled to the sample and hold circuitry. The amplifier is configured to amplify a difference between a sum of the first response voltage potential and the third response voltage potential, and twice the second response voltage potential. A memory device includes an evaluation signal generating circuit configured to provide the evaluation signal, an array of resistance variable memory cells, and the sense circuit. A method includes applying the evaluation signal to the resistance variable memory cell, sampling and holding the response voltage potentials, and discharging the sample and hold circuitry to the amplifier.

Abstract: Certain embodiments of the present invention include an apparatus comprising a charge pump, configured to provide an output voltage at an output node of the charge pump, and a charge pump regulator circuit coupled to the charge pump. One such charge pump regulator circuit is configured to control the charge pump to increase the output voltage during a first period of time. Such a charge pump regulator circuit can also cause a node of a circuit coupled to the output node of the charge pump to reach a target voltage level during a second time period.

Abstract: Sense circuits, memory devices, and related methods are disclosed. A sense circuit includes sample and hold circuitry configured to sample and hold a second response voltage potential, a first response voltage potential, and a third response voltage potential responsive to an evaluation signal applied to a resistance variable memory cell. The sense circuit includes an amplifier operably coupled to the sample and hold circuitry. The amplifier is configured to amplify a difference between a sum of the first response voltage potential and the third response voltage potential, and twice the second response voltage potential. A memory device includes an evaluation signal generating circuit configured to provide the evaluation signal, an array of resistance variable memory cells, and the sense circuit. A method includes applying the evaluation signal to the resistance variable memory cell, sampling and holding the response voltage potentials, and discharging the sample and hold circuitry to the amplifier.