Patents by Inventor Michiaki Sano

Michiaki Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11569139
    Abstract: A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: January 31, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ikue Yokomizo, Michiaki Sano, Kazuto Watanabe, Hajime Yamamoto, Takashi Yamaha, Koichi Ito, Katsuya Kato, Ryo Hiramatsu, Hiroshi Sasaki, Akihiro Tobioka, Liang Li
  • Publication number: 20220352200
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.
    Type: Application
    Filed: November 10, 2021
    Publication date: November 3, 2022
    Inventors: Michiaki SANO, Yusuke MUKAE, Naoki TAKEGUCHI, Yujin TERASAWA, Tatsuya HINOUE, Ramy Nashed Bassely SAID
  • Publication number: 20220328413
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings located in a memory array region and vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and laterally-isolated contact via assemblies located in a contact region that is located adjacent to the memory array region. Each of the laterally-isolated contact via assemblies includes a contact via structure contacting a top surface of a respective one of the electrically conductive layers and a dielectric spacer laterally surrounding the contact via structure. Each contact via structure other than a contact via structure contacting a topmost one of the electrically conductive layers extends through and is laterally surrounded by each electrically conductive layer that overlies the respective electrically conductive layer.
    Type: Application
    Filed: June 20, 2022
    Publication date: October 13, 2022
    Inventors: Tomohiro KUBO, Michiaki SANO
  • Publication number: 20220285234
    Abstract: A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.
    Type: Application
    Filed: March 8, 2021
    Publication date: September 8, 2022
    Inventors: Ikue YOKOMIZO, Michiaki SANO, Kazuto WATANABE, Hajime YAMAMOTO, Takashi YAMAHA, Koichi ITO, Katsuya KATO, Ryo HIRAMATSU, Hiroshi SASAKI, Akihiro TOBIOKA, Liang LI
  • Publication number: 20220189872
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings located in a memory array region and vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and laterally-isolated contact via assemblies located in a contact region. Each of the laterally-isolated contact via assemblies includes a contact via structure contacting a top surface of a respective one of the electrically conductive layers and an insulating spacer laterally surrounding the contact via structure and having an outer surface having a corrugated vertical cross-sectional profile in which first portions of the insulating spacer located at levels of the electrically conductive layers laterally protrude outward relative to second portions of the insulating spacer located at levels of the insulating layers.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Inventors: Michiaki SANO, Koichi ITO
  • Publication number: 20220028879
    Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Inventors: Ryo MOCHIZUKI, Yasuo KASAGI, Michiaki SANO, Junji OH, Yujin TERASAWA, Hiroaki NAMBA
  • Patent number: 11101289
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: August 24, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yu Ueda, Michiaki Sano
  • Publication number: 20210257378
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.
    Type: Application
    Filed: February 19, 2020
    Publication date: August 19, 2021
    Inventors: Yu UEDA, Michiaki SANO
  • Patent number: 10994239
    Abstract: A gas scrubber includes a canister having a rotatable spiral separator which provides a non-linear path configured to be filled with modular adsorbent material portions between a gas inlet and a gas outlet.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 4, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Michiaki Sano, Jo Sato
  • Patent number: 10923496
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: February 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuteru Mushiga, Kenji Sugiura, Akio Nishida, Ryosuke Kaneko, Michiaki Sano
  • Publication number: 20200321324
    Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.
    Type: Application
    Filed: April 2, 2019
    Publication date: October 8, 2020
    Inventors: Michiaki Sano, Takashi YAMAHA, Koichi ITO, Ikue YOKOMIZO, Ryo HIRAMATSU, Kazuto WATANABE, Katsuya KATO, Hajime YAMAMOTO, Hiroshi SASAKI
  • Patent number: 10797035
    Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Michiaki Sano, Takashi Yamaha, Koichi Ito, Ikue Yokomizo, Ryo Hiramatsu, Kazuto Watanabe, Katsuya Kato, Hajime Yamamoto, Hiroshi Sasaki
  • Patent number: 10790296
    Abstract: A bonded structure may be formed by measuring die areas of first semiconductor dies on a wafer at a measurement temperature, generating a two-dimensional map of local target temperatures that are estimated to thermally adjust a die area of each of the first semiconductor dies to a target die area, loading the wafer to a bonding apparatus comprising at least one temperature sensor, and iteratively bonding a plurality of second semiconductor dies to a respective one of the first semiconductor dies by sequentially adjusting a temperature of the wafer to a local target temperature of a respective first semiconductor die that is bonded to a respective one of the second semiconductor dies. An apparatus for forming such a bonded structure may include a computer, a chuck for holding the wafer, a die attachment unit, and a temperature control mechanism.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takashi Yamaha, Katsuya Kato, Kazuto Watanabe, Hajime Yamamoto, Michiaki Sano, Koichi Ito, Ikue Yokomizo, Ryo Hiramatsu, Hiroshi Sasaki
  • Patent number: 10756106
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 25, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Michiaki Sano, Ken Oowada, Zhixin Cui
  • Publication number: 20200219895
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 9, 2020
    Inventors: Mitsuteru MUSHIGA, Kenji SUGIURA, Akio NISHIDA, Ryosuke KANEKO, Michiaki SANO
  • Publication number: 20200168623
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Masatoshi NISHIKAWA, Michiaki SANO, Ken OOWADA, Zhixin CUI
  • Patent number: 10553599
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective memory-level semiconductor channel and a respective memory film. Drain-select-level gate electrodes overlie the alternating stack. Drain-select-level pillar structures extend through a respective one of the drain-select-level gate electrodes. Each drain-select-level semiconductor channel is electrically connected to an underlying one of the memory-level semiconductor channels. A planar insulating spacer layer having a homogeneous composition throughout directly contacts top surfaces of the memory films and bottom surfaces of the drain-select-level gate electrodes.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: February 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhen Chen, Michiaki Sano, Mitsuteru Mushiga
  • Patent number: 10468459
    Abstract: Systems and methods for implementing a memory array comprising vertical bit lines that are connected to different pairs of vertical thin-film transistors (TFTs) are described. A set of vertical TFTs may be formed such that a first TFT and a second TFT are spaced apart by a first separation distance and a third TFT and the second TFT are spaced apart by a second separation distance. The fabrication of the memory array includes forming a layer of conducting material with a thickness that is greater than half of the first separation distance and less than half of the second separation distance and then performing an anisotropic etch to remove portions of the conducting material such that openings in the conducting material are formed between the pairs of vertical TFTs while preventing openings from forming between the vertical TFTs of each pair of vertical TFTs.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: November 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yusuke Oda, Michiaki Sano
  • Publication number: 20190275459
    Abstract: A gas scrubber includes a canister having a rotatable spiral separator which provides a non-linear path configured to be filled with modular adsorbent material portions between a gas inlet and a gas outlet.
    Type: Application
    Filed: March 8, 2018
    Publication date: September 12, 2019
    Inventors: Michiaki SANO, Jo SATO
  • Patent number: 10381322
    Abstract: A first substrate has a first mesa structure that protrudes from a first bonding-side planar surface. A first metal pad structure is embedded within the first mesa structure. A second substrate has a first recess cavity that is recessed from a second bonding-side planar surface. A second metal pad structure is located at a recessed region of the first recess cavity. The first bonding-side planar surface and the second bonding-side planar surface are brought into physical contact with each other, while the first mesa structure is disposed within a volume of the first recess cavity by self-alignment. A gap is provided between the first metal pad structure and the second metal pad structure within a volume of the first recess cavity. A metal connection pad is formed by selectively growing a third metallic material from the first metal pad structure and the second metal pad structure.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yasunobu Azuma, Michiaki Sano