Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.

Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.

Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.

Abstract: A bonded structure may be formed by measuring die areas of first semiconductor dies on a wafer at a measurement temperature, generating a two-dimensional map of local target temperatures that are estimated to thermally adjust a die area of each of the first semiconductor dies to a target die area, loading the wafer to a bonding apparatus comprising at least one temperature sensor, and iteratively bonding a plurality of second semiconductor dies to a respective one of the first semiconductor dies by sequentially adjusting a temperature of the wafer to a local target temperature of a respective first semiconductor die that is bonded to a respective one of the second semiconductor dies. An apparatus for forming such a bonded structure may include a computer, a chuck for holding the wafer, a die attachment unit, and a temperature control mechanism.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective memory-level semiconductor channel and a respective memory film. Drain-select-level gate electrodes overlie the alternating stack. Drain-select-level pillar structures extend through a respective one of the drain-select-level gate electrodes. Each drain-select-level semiconductor channel is electrically connected to an underlying one of the memory-level semiconductor channels. A planar insulating spacer layer having a homogeneous composition throughout directly contacts top surfaces of the memory films and bottom surfaces of the drain-select-level gate electrodes.

Abstract: Systems and methods for implementing a memory array comprising vertical bit lines that are connected to different pairs of vertical thin-film transistors (TFTs) are described. A set of vertical TFTs may be formed such that a first TFT and a second TFT are spaced apart by a first separation distance and a third TFT and the second TFT are spaced apart by a second separation distance. The fabrication of the memory array includes forming a layer of conducting material with a thickness that is greater than half of the first separation distance and less than half of the second separation distance and then performing an anisotropic etch to remove portions of the conducting material such that openings in the conducting material are formed between the pairs of vertical TFTs while preventing openings from forming between the vertical TFTs of each pair of vertical TFTs.

Abstract: A gas scrubber includes a canister having a rotatable spiral separator which provides a non-linear path configured to be filled with modular adsorbent material portions between a gas inlet and a gas outlet.

Abstract: A first substrate has a first mesa structure that protrudes from a first bonding-side planar surface. A first metal pad structure is embedded within the first mesa structure. A second substrate has a first recess cavity that is recessed from a second bonding-side planar surface. A second metal pad structure is located at a recessed region of the first recess cavity. The first bonding-side planar surface and the second bonding-side planar surface are brought into physical contact with each other, while the first mesa structure is disposed within a volume of the first recess cavity by self-alignment. A gap is provided between the first metal pad structure and the second metal pad structure within a volume of the first recess cavity. A metal connection pad is formed by selectively growing a third metallic material from the first metal pad structure and the second metal pad structure.

Abstract: Systems and methods for implementing a memory array comprising vertical bit lines that are connected to different pairs of vertical thin-film transistors (TFTs) are described. A set of vertical TFTs may be formed such that a first TFT and a second TFT are spaced apart by a first separation distance and a third TFT and the second TFT are spaced apart by a second separation distance. The fabrication of the memory array includes forming a layer of conducting material with a thickness that is greater than half of the first separation distance and less than half of the second separation distance and then performing an anisotropic etch to remove portions of the conducting material such that openings in the conducting material are formed between the pairs of vertical TFTs while preventing openings from forming between the vertical TFTs of each pair of vertical TFTs.

Abstract: A wedge-shaped contact region can be employed to provide electrical contacts to multiple electrically conductive layers in a three-dimensional device structure. A cavity including a generally wedge-shaped region and a primary region is formed in a dielectric matrix layer over a support structure. An alternating stack of insulating layers and electrically conductive layers is formed by a series of conformal deposition processes in the cavity and over the dielectric matrix layer. The alternating stack can be planarized employing the top surface of the dielectric matrix layer as a stopping layer. A tip portion of each electrically conductive layer within remaining portions of the alternating stack is laterally offset from the tip of the generally wedge-shaped region by a respective lateral offset distance along a lateral protrusion direction. Contact via structures can be formed on the tip portions of the electrically conductive layers to provide electrical contact.

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, such that each of the first insulating layers and the first electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the first alternating stack that includes the horizontally-extending portions of the first electrically conductive layers, such that each of the memory stack structures comprises a memory film and a vertical semiconductor channel, a mesa structure located over the substrate, such that each respective non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers is located over a sidewall of the mesa structure, and contact structures that contact a respective one of the non-horizontally-extending portions of the first electric

Abstract: Pattern-dependent random deviations in measurement of optimal focus distances can be minimized by separating scan paths into multiple types of scan paths that scan only a respective predetermined image region in semiconductor dies. A substrate including in-process semiconductor dies is coated with a photoresist layer, and is located onto a stage in a lithographic exposure tool. Maps of optimal focus distances are generated by performing optimal focus distance scans that cover a respective subset of image regions having distinct image patterns. The substrate can be leveled with respect to an optics system of the lithographic exposure tool employing a weighted average of multiple maps of optimal focus distances. Once the substrate is leveled on the stage, a lithographic exposure process can be performed with enhanced uniformity in the focus distances across the in-process semiconductor dies.

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. Each of the first insulating layers and the first sacrificial material layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion. Memory stack structures are formed through the horizontally-extending portions of the alternating stack. Regions of the non-horizontally-extending portions of the sacrificial material layers are masked with patterned etch mask portions. Unmasked first regions of the non-horizontally-extending portions of the first sacrificial material layers are selectively recessed, and the sacrificial material layers with electrically conductive layers. Each electrically conductive layer can include a vertical plate region and a protrusion region that protrudes above the vertical plate region and having a narrower lateral dimension that the vertical plate region.

Abstract: A three-dimensional memory device includes an alternating stack of L-shaped insulating layers and L-shaped electrically conductive layers located over a top surface of a substrate, such that each of the L-shaped insulating layers and the L-shaped electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the alternating stack that includes the horizontally-extending portions of the L-shaped electrically conductive layers, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel, dielectric spacers non-horizontally extending between neighboring pairs of a non-horizontally-extending portion of an L-shaped insulating layer and a non-horizontally-extending portion of an L-shaped electrically conductive layer, and contact via structures that contact a respective one of the non-horizontally-extending portions of the L-shaped

Abstract: A method is provided that includes forming a dielectric material and a first sacrificial material above a substrate, forming a second sacrificial material above the substrate and disposed adjacent the dielectric material and the first sacrificial material, forming a first hole in the second sacrificial material, the first hole disposed in a first direction, forming a word line layer above the substrate via the first hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a first portion of a nonvolatile memory material on peripheral sides of the word line layer via the first hole, forming a second hole in the second sacrificial material, forming a second portion of the nonvolatile memory material on a sidewall of the second hole, forming a local bit line in the second hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.

Abstract: A semiconductor device includes a silicon surface, a titanium silicide layer contacting the silicon surface, a first titanium nitride layer located over the titanium silicide layer, a titanium oxynitride layer contacting the first titanium nitride layer, a second titanium nitride layer contacting the titanium oxynitride layer, and a metal fill layer located over the second titanium nitride layer.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.