Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.

Abstract: A multilevel device includes: at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base. Each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack. The base may include a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses. The electrically conductive layers in the stack may be substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base. A first electrically conductive layer in the stack may be a topmost layer in a laterally central portion of a first one of the plurality of recesses.

Abstract: A method of forming sidewall gates for vertical transistors includes depositing a gate dielectric layer over polysilicon channel structures, and depositing a gate polysilicon layer over the gate dielectric. The gate polysilicon layer is then etched back to form separated gate electrodes. Filler portions are then formed between gate electrodes, which are then etched from the top down while their sides are protected.

Abstract: A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.

Abstract: A multilevel device includes: at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base. Each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack. The base may include a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses. The electrically conductive layers in the stack may be substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base. A first electrically conductive layer in the stack may be a topmost layer in a laterally central portion of a first one of the plurality of recesses.

Abstract: A method of forming sidewall gates for vertical transistors includes depositing a gate dielectric layer over polysilicon channel structures, and depositing a gate polysilicon layer over the gate dielectric. The gate polysilicon layer is then etched back to form separated gate electrodes. Filler portions are then formed between gate electrodes, which are then etched from the top down while their sides are protected.

Abstract: A semiconductor structure is fabricated with a void such as a line, contact, via or zia. To prevent slurry particles from falling into and remaining in a void during a chemical-mechanical planarization process, a protective coat is provided in the void to trap the slurry particles and limit an extent to which they can enter the void. A metal layer is provided above the protective coat. Subsequently, the protective coat and trapped slurry particles are removed by cleaning, leaving a void which is substantially free of slurry particles. This is beneficial such as when the void is used as an alignment mark. The protective coat can be an organic layer such as spin-on carbon or i-line photoresist, an ashable material such as amorphous carbon, or a dissolvable and selective material such as SiN.

Abstract: A plasma processing method that makes it possible to remove a photoresist film and fence portion while maintaining a specific shape of the opening is provided. After a wafer W is placed on a lower electrode 106 provided inside a processing chamber 102 of an ashing apparatus 100, power with its frequency set at 60 MHz and its level set at 1 kW and power with its frequency set at 2 MHz and its level set at 250 W are respectively applied to an upper electrode 122 and the lower electrode 106. A processing gas induced into the processing chamber 102 is raised to plasma, a photoresist film 208 at the wafer W is ashed and, at the same time, fence portion 214 formed around the opening of a via hole 210 during the etching process is removed. The level of the power applied to the lower electrode 106 is set equal to or lower than 10 W before the photoresist film 208 is completely removed.

Abstract: An etching method through which the resist-relative selection ratio is improved and the etching shape is also improved, is provided.

Abstract: In a DRAM with a COB (capacitor over bitline) structure where one side of the storage node is approximately equal to the diameter of the contact plug, when the mask is mis-positioned when the storage node is formed, to prevent the underlying oxide film from being exposed at the side surface of the contact hole and to prevent that underlying oxide film from being inadvertently etched during wet etching. Contact plug 7 is formed with oxide film 20 attached on nitride film 5, that acts as an etching stopper during wet etching. By doing this, contact plug 7 is formed projecting upward above underlying oxide film 4 and preferably projecting above nitride film 5. After storage node 10 is formed, when oxide films 8 and 20 are removed by wet etching, underlying oxide film 4 is not exposed at the side surface of contact hole 6 and inadvertent etching of it can be prevented.

Abstract: An etching method through which the resist-relative selection ratio is improved and the etching shape is also improved, is provided. In an etching method for etching an SiO2 layer formed at a wafer W placed inside an airtight processing chamber 104 by inducing a processing gas into the processing chamber 104, the processing gas contains at least C5F8 and CH2F2 and the flow rate ratio of C5F8 and CH2F2 in the processing gas is essentially within the range of 1/4≦(C5F8 flow rate/CH2F2 flow rate)≦1/2. Since the processing gas contains C5F8 and CH2F2, the resist-relative selection ratio can be improved. In addition, by setting the flow rate ratio of C5F8 and CH2F2 essentially equal to or larger than 1/4, deformation of grooves due to longitudinal streaking or waviness can be eliminated, whereas by setting the flow rate ratio of C5F8 and CH2F2 essentially equal to or smaller than 1/2, deformation of grooves attributable to bowing can be eliminated.

Abstract: In a DRAM with a COB (capacitor over bitline) structure where one side of the storage node is approximately equal to the diameter of the contact plug, when the mask is mis-positioned when the storage node is formed, to prevent the underlying oxide film from being exposed at the side surface of the contact hole and to prevent that underlying oxide film from being inadvertently etched during wet etching. Contact plug 7 is formed with oxide film 20 attached on nitride film 5, that acts as an etching stopper during wet etching. By doing this, contact plug 7 is formed projecting upward above underlying oxide film 4 and preferably projecting above nitride film 5. After storage node 10 is formed, when oxide films 8 and 20 are removed by wet etching, underlying oxide film 4 is not exposed at the side surface of contact hole 6 and inadvertent etching of it can be prevented.