Patents by Inventor Michiaki Sano

Michiaki Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160148835
    Abstract: A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: Seiji SHIMABUKURO, Hiroaki IUCHI, Michiaki SANO, Naoki TAKEGUCHI
  • Publication number: 20160126455
    Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 5, 2016
    Inventors: Eiji Hayashi, Naohito Yanagida, Michiaki Sano, Akira Nakada
  • Publication number: 20160126292
    Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 5, 2016
    Inventors: Naohito Yanagida, Cheng Feng, Michiaki Sano, Akira Nakada, Steven J. Radigan, Eiji Hayashi
  • Publication number: 20160111439
    Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 21, 2016
    Inventors: Masanori Tsutsumi, Hiroshi Sasaki, Hiroyuki Ogawa, Michiaki Sano, Masato Miyamoto, Kensuke Yamaguchi, Seiji Shimabukuro
  • Patent number: 9305937
    Abstract: A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: April 5, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Masanori Tsutsumi, Hiroshi Sasaki, Hiroyuki Ogawa, Michiaki Sano, Masato Miyamoto, Kensuke Yamaguchi, Seiji Shimabukuro
  • Publication number: 20160093524
    Abstract: A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of alternating sacrificial layers and insulating layers located over a major surface of a substrate. A contact mask having contact mask openings is provided over the stack, and a first over mask having first over mask openings is provided over the contact mask. A subset of the contact mask openings is substantially aligned with the first over mask openings. Contact openings are formed through the stack, wherein each of the contact openings extends substantially perpendicular to the major surface of the substrate to a respective one of the sacrificial layers. A plurality of electrically conductive via contacts is formed in the plurality of the contact openings.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Inventors: Keisuke Izumi, Michiaki Sano, Hiroshi Sasaki
  • Publication number: 20160093626
    Abstract: A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of a plurality of alternating sacrificial layers and insulator layers located over a major surface of a substrate. A contact mask with at least one contact mask opening and at least one first terrace mask opening is provided over the stack, where the at least one first terrace mask opening is larger than the at least one contact mask opening. At least one first contact opening and at least one first terrace opening are simultaneously formed extending substantially perpendicular to the major surface of the substrate through the stack to a first sacrificial layer by etching a portion of the stack through the at least one contact mask opening and the at least one first terrace mask opening. A first electrically conductive via contact is deposited in the at least one first contact opening.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Inventors: Keisuke Izumi, Michiaki Sano, Hiroshi Sasaki
  • Publication number: 20160064281
    Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 3, 2016
    Inventors: Keisuke Izumi, Naohito Yanagida, Michiaki Sano, Takehiro Yamazaki, Hiroaki Iuchi, Akio Yanai, Genta Mizuno, Minoru Yamaguchi
  • Patent number: 9230905
    Abstract: A multilevel device includes: at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base. Each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack. The base may include a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses. The electrically conductive layers in the stack may be substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base. A first electrically conductive layer in the stack may be a topmost layer in a laterally central portion of a first one of the plurality of recesses.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: January 5, 2016
    Assignee: SANDISK 3D LLC
    Inventors: Seje Takaki, Michiaki Sano, Zhen Chen
  • Patent number: 9177964
    Abstract: A method of forming sidewall gates for vertical transistors includes depositing a gate dielectric layer over polysilicon channel structures, and depositing a gate polysilicon layer over the gate dielectric. The gate polysilicon layer is then etched back to form separated gate electrodes. Filler portions are then formed between gate electrodes, which are then etched from the top down while their sides are protected.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: November 3, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Akira Nakada, Michiaki Sano, Naohito Yanagida, Teruyuki Mine
  • Publication number: 20150249143
    Abstract: A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 3, 2015
    Applicant: SanDisk 3D LLC
    Inventors: Michiaki Sano, Kensuke Yamaguchi, Akira Nakada, Naohito Yanagida
  • Publication number: 20150194380
    Abstract: A multilevel device includes: at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base. Each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack. The base may include a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses. The electrically conductive layers in the stack may be substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base. A first electrically conductive layer in the stack may be a topmost layer in a laterally central portion of a first one of the plurality of recesses.
    Type: Application
    Filed: January 8, 2014
    Publication date: July 9, 2015
    Applicant: SanDisk 3D LLC
    Inventors: Seje Takaki, Michiaki Sano, Zhen Chen
  • Publication number: 20150162338
    Abstract: A method of forming sidewall gates for vertical transistors includes depositing a gate dielectric layer over polysilicon channel structures, and depositing a gate polysilicon layer over the gate dielectric. The gate polysilicon layer is then etched back to form separated gate electrodes. Filler portions are then formed between gate electrodes, which are then etched from the top down while their sides are protected.
    Type: Application
    Filed: December 6, 2013
    Publication date: June 11, 2015
    Applicant: SanDisk 3D LLC
    Inventors: Akira Nakada, Michiaki Sano, Naohito Yanagida, Teruyuki Mine
  • Publication number: 20110244683
    Abstract: A semiconductor structure is fabricated with a void such as a line, contact, via or zia. To prevent slurry particles from falling into and remaining in a void during a chemical-mechanical planarization process, a protective coat is provided in the void to trap the slurry particles and limit an extent to which they can enter the void. A metal layer is provided above the protective coat. Subsequently, the protective coat and trapped slurry particles are removed by cleaning, leaving a void which is substantially free of slurry particles. This is beneficial such as when the void is used as an alignment mark. The protective coat can be an organic layer such as spin-on carbon or i-line photoresist, an ashable material such as amorphous carbon, or a dissolvable and selective material such as SiN.
    Type: Application
    Filed: April 1, 2010
    Publication date: October 6, 2011
    Inventor: Michiaki Sano
  • Patent number: 6743730
    Abstract: A plasma processing method that makes it possible to remove a photoresist film and fence portion while maintaining a specific shape of the opening is provided. After a wafer W is placed on a lower electrode 106 provided inside a processing chamber 102 of an ashing apparatus 100, power with its frequency set at 60 MHz and its level set at 1 kW and power with its frequency set at 2 MHz and its level set at 250 W are respectively applied to an upper electrode 122 and the lower electrode 106. A processing gas induced into the processing chamber 102 is raised to plasma, a photoresist film 208 at the wafer W is ashed and, at the same time, fence portion 214 formed around the opening of a via hole 210 during the etching process is removed. The level of the power applied to the lower electrode 106 is set equal to or lower than 10 W before the photoresist film 208 is completely removed.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: June 1, 2004
    Assignee: Tokyo Electron Limited
    Inventor: Michiaki Sano
  • Publication number: 20030006216
    Abstract: An etching method through which the resist-relative selection ratio is improved and the etching shape is also improved, is provided.
    Type: Application
    Filed: August 20, 2002
    Publication date: January 9, 2003
    Inventors: Kenji Adachi, Michiaki Sano
  • Patent number: 6483141
    Abstract: In a DRAM with a COB (capacitor over bitline) structure where one side of the storage node is approximately equal to the diameter of the contact plug, when the mask is mis-positioned when the storage node is formed, to prevent the underlying oxide film from being exposed at the side surface of the contact hole and to prevent that underlying oxide film from being inadvertently etched during wet etching. Contact plug 7 is formed with oxide film 20 attached on nitride film 5, that acts as an etching stopper during wet etching. By doing this, contact plug 7 is formed projecting upward above underlying oxide film 4 and preferably projecting above nitride film 5. After storage node 10 is formed, when oxide films 8 and 20 are removed by wet etching, underlying oxide film 4 is not exposed at the side surface of contact hole 6 and inadvertent etching of it can be prevented.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Michiaki Sano
  • Patent number: 6461962
    Abstract: An etching method through which the resist-relative selection ratio is improved and the etching shape is also improved, is provided. In an etching method for etching an SiO2 layer formed at a wafer W placed inside an airtight processing chamber 104 by inducing a processing gas into the processing chamber 104, the processing gas contains at least C5F8 and CH2F2 and the flow rate ratio of C5F8 and CH2F2 in the processing gas is essentially within the range of 1/4≦(C5F8 flow rate/CH2F2 flow rate)≦1/2. Since the processing gas contains C5F8 and CH2F2, the resist-relative selection ratio can be improved. In addition, by setting the flow rate ratio of C5F8 and CH2F2 essentially equal to or larger than 1/4, deformation of grooves due to longitudinal streaking or waviness can be eliminated, whereas by setting the flow rate ratio of C5F8 and CH2F2 essentially equal to or smaller than 1/2, deformation of grooves attributable to bowing can be eliminated.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: October 8, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Kenji Adachi, Michiaki Sano
  • Publication number: 20020058379
    Abstract: In a DRAM with a COB (capacitor over bitline) structure where one side of the storage node is approximately equal to the diameter of the contact plug, when the mask is mis-positioned when the storage node is formed, to prevent the underlying oxide film from being exposed at the side surface of the contact hole and to prevent that underlying oxide film from being inadvertently etched during wet etching. Contact plug 7 is formed with oxide film 20 attached on nitride film 5, that acts as an etching stopper during wet etching. By doing this, contact plug 7 is formed projecting upward above underlying oxide film 4 and preferably projecting above nitride film 5. After storage node 10 is formed, when oxide films 8 and 20 are removed by wet etching, underlying oxide film 4 is not exposed at the side surface of contact hole 6 and inadvertent etching of it can be prevented.
    Type: Application
    Filed: August 30, 1999
    Publication date: May 16, 2002
    Inventor: MICHIAKI SANO